48 skills found · Page 1 of 2
Nic30 / HdlConvertorFast Verilog/VHDL parser preprocessor and code generator for C++/Python based on ANTLR4
veripool / Verilog PerlVerilog parser, preprocessor, and related tools for the Verilog-Perl package
ben-marshall / Verilog ParserA Flex/Bison Parser for the IEEE 1364-2001 Verilog Standard.
ben-marshall / Verilog Vcd ParserA parser for Value Change Dump (VCD) files as specified in the IEEE System Verilog 1800-2012 standard.
OpenTimer / Parser VerilogA Standalone Structural Verilog Parser
anikau31 / Systemc ClangThis is a Clang tool that parses SystemC models, and synthesizes Verilog from it.
yellekelyk / PyVerilogPython-based Verilog Parser (currently Netlist only)
najaeda / Naja VerilogA standalone structural (gate-level) verilog parser
tomahawkins / VerilogA Verilog parser for Haskell.
jimwang99 / Parser For Chip DesignA set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
cclienti / SvmoduleSystemVerilog & Verilog Module I/O parser and printer
codinuum / CcaCode Continuity Analysis Framework
tcr / Rust VerilogVerilog parsing and generator crate.
davidkebo / Verilog ParserA verilog parser
FranklineMisango / Hft Fpga AcceleratorFPGA & CuDNN/CUDA infrastructure for low-latency algorithmic trading. Implements market data parsing, order book management, and strategy logic in Verilog/VHDL. Designed for Xilinx/Intel FPGAs with PCIe/10G networking support.
jaijeet / VAPPThe Berkeley Verilog-A Parser and Processor
sepandhaghighi / VerilogparserSimple Verilog Parser In Python
xprova / Netlist GraphJava library for parsing and manipulating graph representations of gate-level Verilog netlists
rochus-keller / VerilogThis is the Verilog 2005 parser used by VerilogCreator
gburdell / NldbVerilog netlist parser/database (derived from http://nldb.sourceforge.net)
