18 skills found
bperez77 / Xilinx AxidmaA zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
robseb / Rsyocto🤖 SoCFPGA: Open-Source Embedded Linux Distribution with a highly flexible build system, developed for Intel (ALTERA) SoC-FPGAs (Cyclone V & Arria 10)
zkf0100007 / EagleSDR PiEagleSDR Pi is a single board SDR Pplatform. It includes a Xilinx Zynq-7020, AD9363/AD9361/AD9364, 512 MByte DDR3L memory, USB OTG port, USB-JTAG/UART port, Ethernet port, 16 MByte Flash memory and MicroSD for configuration and operation. The EagleSDR Pi features the Zynq SoC product from Xilinx, which contains an ARM® Cortex®-A9 core. This makes the EagleSDR Pi extremely flexible, allowing users to take advantage of ARM, and possibly the FPGA fabric as well.
robseb / HPS2FPGAmappingSoCFPGA: Mapping HPS Peripherals, like I²C or CAN, over the FPGA fabric to FPGA I/O and using embedded Linux to control them (Intel Cyclone V)
andrewboutros / Rad FlowThe RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.
robseb / Meta IntelfpgaYocto Project BSP meta-layer for Intel (ALTERA) SoC-FPGAs (SoCFPGA) - with step by step guide
FPGA-MAFIA / Fpga MafiaDesigning a Multi-Agent Fabric Integration Architecture to run on de10-lite FPGA.
Hossamomar / EM070 New FPGA Family For CNN Architectures High Speed Soft Neuron DesignWho doesn’t dream of a new FPGA family that can provide embedded hard neurons in its silicon architecture fabric instead of the conventional DSP and multiplier blocks? The optimized hard neuron design will allow all the software and hardware designers to create or test different deep learning network architectures, especially the convolutional neural networks (CNN), more easily and faster in comparing to any previous FPGA family in the market nowadays. The revolutionary idea about this project is to open the gate of creativity for a precise-tailored new generation of FPGA families that can solve the problems of wasting logic resources and/or unneeded buses width as in the conventional DSP blocks nowadays. The project focusing on the anchor point of the any deep learning architecture, which is to design an optimized high-speed neuron block which should replace the conventional DSP blocks to avoid the drawbacks that designers face while trying to fit the CNN architecture design to it. The design of the proposed neuron also takes the parallelism operation concept as it’s primary keystone, beside the minimization of logic elements usage to construct the proposed neuron cell. The targeted neuron design resource usage is not to exceeds 500 ALM and the expected maximum operating frequency of 834.03 MHz for each neuron. In this project, ultra-fast, adaptive, and parallel modules are designed as soft blocks using VHDL code such as parallel Multipliers-Accumulators (MACs), RELU activation function that will contribute to open a new horizon for all the FPGA designers to build their own Convolutional Neural Networks (CNN). We couldn’t stop imagining INTEL ALTERA to lead the market by converting the proposed designed CNN block and to be a part of their new FPGA architecture fabrics in a separated new Logic Family so soon. The users of such proposed CNN blocks will be amazed from the high-speed operation per seconds that it can provide to them while they are trying to design their own CNN architectures. For instance, and according to the first coding trial, the initial speed of just one MAC unit can reach 3.5 Giga Operations per Second (GOPS) and has the ability to multiply up to 4 different inputs beside a common weight value, which will lead to a revolution in the FPGA capabilities for adopting the era of deep learning algorithms especially if we take in our consideration that also the blocks can work in parallel mode which can lead to increasing the data throughput of the proposed project to about 16 Tera Operations per Second (TOPS). Finally, we believe that this proposed CNN block for FPGA is just the first step that will leave no areas for competitions with the conventional CPUs and GPUs due to the massive speed that it can provide and its flexible scalability that it can be achieved from the parallelism concept of operation of such FPGA-based CNN blocks.
ShonTaware / FPGA Design Fabric ArchitectureThis repository contains all the information studied and created during the FPGA - Fabric, Design and Architecture workshop. It is primarily focused on a complete FPGA flow using the maximum open-source tools.
mcleod-ideafix / Simple Sdram ControllerA very simple SDRAM controller for FPGA written in Verilog. It exposes a SRAM-like interface to the rest of the FPGA fabric
robseb / Django2FPGAdemoDemonstration how to build a Management Web interface to interact with the FPGA fabric and change the FPGA configuration with the Django Framework
pratheepjoe / Hw Sw Co Design For CryptographyThe objective of this course is to build knowledge and skills necessary for efficient implementations of cryptographic primitives on reconfigurable hardware. The implementation platform will be a field programmable gate array (FPGA) containing a general purpose processor and additional reconfigurable fabric for implementations of custom hardware accelerators. In the studio format,team projects require designof selected cryptographic primitives followed bycomparisonand contrastof various implementation alternatives, such assoftware, custom FPGA hardware, and hybrid hardware-software co-design. Project teams are ideally composed of one Computer Engineering student and one Software Engineering or Computer Science student. Computer Engineering students lead the hardware design portions of each project,and Software Engineering and Computer Science students lead the software development portions. Topics may includebinary finite field arithmetic, block ciphers,
steenl / PortAlchemyFocus on UALink usage cases interconnecting CPUs, GPUs, and memory pools. Leveraged from prior NetFPGA10GbE work, we scale to 200+Gbps with prioritized queueing between customized RISC-V and memory targets on real FPGAs and fabrics.
navinkumar357 / FFT Calculation Using FPGA FabricsVerilog, HLS, C, C++, Zynq series.
StephenMoreOSU / Rad GenRAD-Gen is a tool for silicon area/timing/power implementation results of hard (ASIC) components, FPGA fabric circuitry, and circuit modeling of 3D devices/packaging
gabrielkulp / Fpga VariationSome gateware that aims to find manufacturing variation that causes performance differences across FPGA fabric.
panda5mt / Qf Wbfpga PioQuickLogic EOS S3:Cortex-M4 to FPGA Fabric via WISHBONE bus Sample Code with 8bit CAMERA-IF
bluez-sh / Axiom Beta RfdevA Linux Kernel Driver for programming/debugging the Lattice MachXO2 FPGAs (used as routing fabrics) in AXIOM Beta Main Board
