64 skills found · Page 1 of 3
msoos / CryptominisatAn advanced SAT solver
potatoshred / HUST ONLINEHUST华中科技大学CS23课程记录：C语言程序设计、计算思维、微积分、线性代数、数据结构data structure、程序设计sat dpll sudoku、离散数学、军事理论、CPP/C++、习思想、人工智能导论、大学物理、数字电路、数电、电路理论、离散数学、算法设计与分析algorithm、马原、计算机系统基础ICS、计算机组成原理、计组、java、verilog、信号与系统基础、数据库database、毛概
ZipCPU / DpllA collection of phase locked loop (PLL) related projects
Time-Appliances-Project / SwitchberrySwitchberry is a Raspberry Pi Compute Module–controlled Ethernet switching + timing platform built around a Microchip KSZ9567 and a Renesas 8A34004 ClockMatrix DPLL. It’s designed for PTP / SyncE / timing lab workflows while staying flexible enough to run as a compact managed switch/router with precise timing I/O.
jddes / Frequency Comb DPLLDigital Phase-locked-loop software for Locking a Frequency Comb using a Red Pitaya
sukrutrao / SAT Solver DPLLA simple SAT solver that implements the DPLL algorithm with unit resolution
dbueno / FunsatAn efficient, embeddable DPLL SAT solver in Haskell
Koukyosyumei / Gymbogradient-based symbolic execution engine implemented from scratch
Billy1900 / DPLL Algorithm华中科技大学数据结构课程设计2018 An algorithm to solve SAT problem
MorrisMA / 1PPS DPLLDPLL for phase-locking to 1PPS signal
dynaroars / NeuralsatDPLL(T)-based Verification tool for DNNs
Starrylay / Awesome HUST CS SAT DPLL华中科技大学19级程序设计综合课程设计/数独求解器/数据结构课程设计/带有图形界面Easy-X
charliermarsh / OCaml SAT SolversAn OCaml implementation of the DPLL algorithm for solving SAT instances. Uses nothing beyond the OCaml List library.
oahzxl / SatDpllBaseline基于SAT的二进制数独游戏求解程序-基准版
jsloan256 / DpllA simple SystemVerilog digital phase-locked loop based (roughly) on TI's SDLA005B application note. The design includes a SystemVerilog testbench demonstrating a full generator, driver, monitor, and scoreboard testbench environment.
marcmelis / Dpll SatSimple Python implementation of a Complete/Systematic SAT Solver with the DPLL algorithm
asgordon / DPLLBoolean satisfiability for propositional logic in Python
NickLee2050 / HustProgramDesignProgram Design affiliated to General Course Design of CSE College, HUST, for students enrolled in 2018.
jiajingyyyyyy / HUST SAT Solver Embedded In Hanidoku华中科技大学程序设计综合课设，基于DPLL算法的SAT求解器+蜂窝数独 / stater
AlbertYang0112 / DPLL FPGAA digital phase-locked loop implemented on Spartan-6
