26 skills found
Xilinx / Vitis AIVitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
triSYCL / SyclSYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
Xilinx / Xup Compute AccelerationHands-on experience using the Vitis unified software platform with Xilinx FPGA hardware
lvgl / Lv Port Xilinx Zedboard VitisThis repository contains a template AMP project for the Zedboard using VGA, FreeRTOS, LVGL and USB peripherals
farbius / Linux Vitis ZynqBuilding Linux System Software with Xilinx Vitis 2022.1 and Buildroot for Zynq 7000 / ZynqMP platforms.
dsa-shua / FPGA SystolicArrayWorking 8x8 systolic array hardware implemented in Xilinx Vivado, operated and controlled in software using Xilinx Vitis
hajin-kim / FPGA Tutorial With HLSFPGA with Xilinx Vitis HLS, Vivado, Vitis, and ZYNQ board. Working with HLS, Matrix Multiplier with HLS
gewuek / Flower Classification Vai Tf Numpy ArrayThe project is a simple example about how to use TensorFlow to train a ConNet model from labeled dataset and then use Vitis AI tools to deploy the model into Xilinx FPGA(ZCU102 board). To make it easier to deploy with Vitis AI. I just use numpy array as input data and OpenCV function to open images. And there is backup for DNNDK3.1 tag
chuchu0512 / Image Processing On ZCU104Using Xilinx Vitis, Vivado and Vitis HLS design program and running on Xilinx ZCU104 board
TurakhiaLab / DP HLSHLS-based framework to accelerate the implementation of 2-D DP kernels on FPGA
miya4649 / Vitis KV260 KR260 TemplateAn bare metal application project template for Vitis unified IDE to start development easily (Support for AMD (Xilinx) Kria KV260, KR260)
nodamushi / Vivado Cmake ModuleCMake for Xilinx Vivado/Vitis
gewuek / Flower Classification Vai Tf DatasetThe project show how to quick train a model and deploy it on Xilinx FPGA using TensorFlow and Vitis AI. It uses tf.data.Dataset API to handle input data, so that the input function need to be rewritten. And there is a backup for DNNDK 3.1 tag
rockyco / Fft Ip TestCritical bug in AMD/Xilinx Vitis HLS FFT IP (float, pipelined streaming)
zst123 / Pynq Sha256 HlsDeploy SHA256 algorithm accelerated on the Xilinx Kria using PYNQ & Vitis HLS
jimw567 / Xbutil GuiA Python Tkinter GUI for Xilinx Vitis xbutil program
trickortreat999 / Segmentation语义分割新模型（Semantic segmentation）应用非常广泛，如抖音里的换衣服，医疗里的病灶和血管分割，自动驾驶的道路分割。语义分割技术近年来发展迅速，而现成的Xilinx model zoo里segmentation模型仅有2016年发表的特征金字塔网络FPN，我们将在本项目中研究此后出现的新的语义分割模型Mask R-CNN ，谷歌的DeepLab，路径聚合网络PANET,环境编码网络EncNet,设计一种轻量级模型能够在FPGA有着比FPN更优性能的模型，又因为Xilinx FPGA的DPU设计限制，我们必须让这种新模型能够用Vitis AI软件转化为FPGA能够接受的定点模型，并用cityscapes数据集进行重新训练和优化参数，最后在ultra96开发板上进行性能测试和进一步优化，获得卓越性能。
KeitetsuWorks / Vitis DockerDocker Image for Xilinx Vitis Unified Software Platform Installation
gpanders / Vitis ExampleExample project for Xilinx Vitis
Freed-Wu / Xilinx Language Serverlanguage server and vim plugin for xilinx vivado and vitis
