41 skills found · Page 1 of 2
tdeekens / Flopflip🎚Flip or flop features in your React application in real-time backed by flag provider of your choice 🚦
snbk001 / Verilog Design ExamplesVerilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
sky-ecosystem / Auction KeeperMaker Keeper Framework: Keeper to participate in `flip`, `flop` and `flap` auctions in multicollateral Dai.
nanoporetech / FlappieFlip-flop basecaller for Oxford Nanopore reads
TheByteAttic / CERBERUS2100The amazing multi-processor 8-bit microcomputer, featuring Z80, 6502 and AVR processors. Built with CPLDs, CERBERUS 2100™ is fully programmable even with respect to its hardware, at the individual gate and flip-flop level.
mattvenn / Flipflop DemoFlip flop setup, hold & metastability explorer tool
SimonBuxx / LogiJSDiscover and create logic circuits
snbk001 / 100DaysofRTL100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
mattvenn / LogLUTsTool to parse yosys and nextpnr logfiles to then plot LUT, flip-flop and maximum frequency stats as your project progresses.
charkster / Spi Slave VerilogSPI bus slave and flip-flop register memory map implemented in Verilog 2001 for FPGAs
vsdip / VsdsramAn SRAM IP Uniquely designed with open source tools. Static RAM is a type of random-access memory that uses latching circuitry (flip-flop) to store each bit. The size of SRAM specs is 32kbit/4k bytes with 1.8v. A 6T SRAM pairs up with two access transistors for read, write state and cross coupled inverter to hold/regenerate the state.
sinkswim / VhdllibMy own VHDL components library. Anything from a flip flop to an ALU.
agausmann / FlipFlopA digital logic simulator built on simple rules.
piyalidas10 / Quiz Flip Flop AngularQuiz game with Flip Flop animation in Angular 12
xprova / XprovaFormal verification engine for Verilog with built-in support for simulating flip-flop metastability
hosseinfani / Digital OdysseyMaterials for the Computer Science course, Digital Design (Logic Circuits)
FarshidKeivanian / Multi Objective Optimization Of MOSFETs Channel Widths And Supply Voltage In The Proposed Dual Edge FuzzyNSGA-II-Algorithm (Fuzzy adaptive optimisation method)
utkarshkukreti / Flip Flop.rsThis library implements the [flip-flop operator from Perl and Ruby](https://en.wikipedia.org/wiki/Flip-flop_(programming)) as a Rust macro.
samuelbigos / Todd The CaverAs Todd, flip-flop your way to discovering mysteries in the depths. Ludum Dare 48.
JanBurp / MorphaLogicAn eurorack logic module with several logic functions and a clock divider mode. Build around an arduino nano. So could be reprogrammed.
