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100DaysofRTL

100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore

Install / Use

/learn @snbk001/100DaysofRTL

Related Skills

View on GitHub
GitHub Stars39
CategoryDesign
Updated2mo ago
Forks3

Languages

SystemVerilog

Security Score

80/100

Audited on Jan 22, 2026

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