92 skills found · Page 1 of 4
chipsalliance / ChiselChisel: A Modern Hardware Design Language
ucb-bar / DsptoolsA Library of Chisel3 Tools for Digital Signal Processing
SingularityKChen / Dl AcceleratorDeep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
MaxXSoft / FuxiFuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.
LoveLonelyTime / BergamotAn exquisite superscalar RV32GC processor.
freechipsproject / DiagrammerProvides dot visualizations of chisel/firrtl circuits
agile-hw / LecturesLectures for the Agile Hardware Design course in Jupyter Notebooks
microdynamics-cpu / Tree Core IdeThe next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
howardlau1999 / YatcpuYet another toy CPU.
sysprog21 / Ca2025 MycpuRISC-V CPU Labs in Chisel
rhysd / Riscv32 Cpu ChiselLearning how to make RISC-V 32bit CPU with Chisel
rameloni / Tywaves ChiselA repository that implements Tywaves: enabling a type-based waveform debugging for Chisel and Tydi-Chisel. Mapping from Chisel level code to values dumped by simulators is now possible thanks to Tywaves!
SYSU-SCC / Yatcpu DocsDocumentation for YatCPU
meton-robean / Vector MulAdd Acceleratorvector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
thoughtworks / Hardposit Chisel3Chisel library for Unum Type-III Posit Arithmetic
panda5mt / KyogenRVThe Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.
rgb000000 / Eyeriss Chisel3eyeriss-chisel3
whutddk / Rift2CoreBased on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.
jiegec / Fpu WrappersWrappers for open source FPU hardware implementations.
Lampro-Mellon / QuasarQuasar 2.0: Chisel equivalent of SweRV-EL2
