14 skills found
OSVVM / AXI4AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
mmxsrup / Axi4 InterfaceAXI4 and AXI4-Lite interface definitions
airhdl / Spi To Axi BridgeAn SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
JoseIuri / Axi4lite2uartThis IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
arhamhashmi01 / Axi4 LiteThis repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
otto-tom / Can Axi4liteCAN-bus Controller with AXI4-lite Interface
dpretet / MeduramMulti-port BRAM IP for ASIC and FPGA
keyonhome / AXI4 LiteIPA verilog FPGA Interface for AXI4_Lite from Slave side
smartfoxdata / Axi4lite GpioGeneral purpose IO port with AXI4-Lite interface
krailis / Zynq Axi TutorialA tutorial on the usage of AXI4-Lite and AXI4-Stream Interfaces on HW Accelerators generated through High-Level Synthesis (HLS)
bnewbold / Axi Lite GenAXI4-Lite FPGA interface, docs, and util generator
dighrasker / MultiCore L2 CacheA UVM-based verification environment for a multi-core, write-back L2 cache on 32-bit RISC-V, enforcing MESI coherence with L1 caches and interfacing to DRAM over AXI4-Lite.
Ammar-Bin-Amir / AXI4RTL Design of AXI4 Bus Protocol followed by AXI4-Lite Bus Protocol and Handshaking Communication Principle
ELAZARBELENKY / Sha 256 HW AcceleratorHardware-accelerated SHA-256 implemented on a PYNQ-Z2 FPGA. Includes custom SystemVerilog IP, AXI4-Lite/DMA integration, and Python/Jupyter interface. Achieves faster hashing for large data vs CPU
