161 skills found · Page 1 of 6
pulp-platform / AxiAXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
chipsalliance / Cores VeeR EH1VeeR EH1 core
taichi-ishitani / Tvip AxiAMBA AXI VIP
Hanley-Yao / Zynq7010 Eink Controller这是一个基于Zynq7010的Eink控制器 在ED097TC2上高质量显示帧数高达10FPS
chipsalliance / Cores VeeR EL2VeeR EL2 Core
WangXuan95 / FPGA UARTThis repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调试器。
adki / Gen Amba 2021AMBA bus generator including AXI4, AXI3, AHB, and APB
dpretet / Axi CrossbarAn AXI4 crossbar implementation in SystemVerilog
WangXuan95 / FPGA DDR SDRAMAn FPGA-based DDR1 controller. 基于FPGA的DDR1控制器，为低端FPGA嵌入式系统提供廉价、大容量的存储。
taichi-ishitani / TnocNetwork on Chip Implementation written in SytemVerilog
aignacio / RavenocRaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
OSVVM / AXI4AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
loykylewong / FPGA Application Development And Simulation《FPGA应用开发和仿真》（机械工业出版社2018年第1版 ISBN:9787111582786）的源码。Source Code of the book FPGA Application Development and Simulation(CHS).
lizhirui / AXI SDCard High Speed ControllerA SDCard Controller Based AXI4 Bus with SDIO 4-wire 50MHz Mode(Max Rate 23MB/s)
Verdvana / AXI4 InterconnectAXI总线连接器
ultraembedded / Core Sdram Axi4SDRAM controller with AXI4 interface
mmxsrup / Axi4 InterfaceAXI4 and AXI4-Lite interface definitions
ultraembedded / Core Ft60x AxiFTDI FT600 SuperSpeed USB3.0 to AXI bus master
OVGN / OpenHBMCOpen-source high performance AXI4-based HyperRAM memory controller
ultraembedded / Core Dvi FramebufferMinimal DVI / HDMI Framebuffer
