AXI SystemVerilog Modules for High-Performance On-Chip Communication

This repository provides modules to build on-chip communication networks adhering to the [AXI4 or AXI4-Lite standards][AMBA 5 Spec]. For high-performance communication, we implement AXI4+ATOPs from AXI5. For lightweight communication, we implement AXI4-Lite. We aim to provide a complete end-to-end communication platform, including endpoints such as DMA engines and on-chip memory controllers.

Our design goals are:

• Topology Independence: We provide elementary building blocks such as protocol multiplexers and demultiplexers that allow users to implement any network topology. We also provide commonly used interconnecting components such as a crossbar.
• Modularity: We favor design by composition over design by configuration where possible. We strive to apply the Unix philosophy to hardware: make each module do one thing well. This means you will more often instantiate our modules back-to-back than change a parameter value to build more specialized networks.
• Fit for Heterogeneous Networks: Our modules are parametrizable in terms of data width and transaction concurrency. This allows to create optimized networks for a wide range of performance (e.g., bandwidth, concurrency, timing), power, and area requirements. We provide modules such as data width converters and ID width converters that allow to join subnetworks with different properties, creating heterogeneous on-chip networks.
• Full AXI Standard Compliance.
• Compatibility with a wide range of (recent versions of) EDA tools and implementation in standardized synthesizable SystemVerilog.

The design and microarchitecture of the modules in this repository is described in this paper (preprint). If you use our work in your research, please cite it.

List of Modules

In addition to the documents linked in the following table, we are setting up documentation auto-generated from inline docstrings. (Replace master in that URL with a tag to get the documentation for a specific version.)

| Name | Description | Doc | |-------------------------------------------------------------|------------------------------------------------------------------------------------------------------|----------------------------------| | axi_atop_filter | Filters atomic operations (ATOPs), i.e., write transactions that have a non-zero aw_atop value. | | | axi_burst_splitter | Split AXI4 burst transfers into single-beat transactions. | | | axi_burst_splitter_gran | Split AXI4 burst transfers into transactions of runtime-configurable granularity. | | | axi_burst_unwrap | Convert AXI4 wrapping burst transfers into up to two incremental bursts. | | | axi_cdc | AXI clock domain crossing based on a Gray FIFO implementation. | | | axi_cut | Breaks all combinatorial paths between its input and output. | | | axi_delayer | Synthesizable module which can (randomly) delays AXI channels. | | | axi_demux_simple | Demux without spill registers. | Doc | | axi_demux | Demultiplexes an AXI bus from one slave port to multiple master ports. | Doc | | axi_dw_converter | A data width converter between AXI interfaces of any data width. | | | axi_dw_downsizer | A data width converter between a wide AXI master and a narrower AXI slave. | | | axi_dw_upsizer | A data width converter between a narrow AXI master and a wider AXI slave. | | | axi_err_slv | Always responds with an AXI decode/slave error for transactions which are sent to it. | | | axi_fifo | A Fifo for each AXI4 channel to buffer requests. | | | axi_from_mem | This module acts like an SRAM and makes AXI4 requests downstream. | | | axi_id_prepend | This module prepends/strips the MSB from the AXI IDs. | | | axi_id_remap | Remap AXI IDs from wide IDs at the slave port to narrower IDs at the master port. | [Doc][doc.axi_id_remap] | | axi_id_serialize | Reduce AXI IDs by serializing transactions when necessary. | [Doc][doc.axi_id_serialize] | | axi_interleaved_xbar | Interleaved version of the crossbar. This module is experimental; use at your own risk. | | | axi_intf | This file defines the interfaces we support. | | | axi_inval_filter | Listens to AXI4 AW channel and issues single cacheline invalidations. | | | axi_isolate | A module that can isolate downstream slaves from receiving new AXI4 transactions. | | | axi_iw_converter | Convert between any two AXI ID widths. | [Doc][doc.axi_iw_converter] | | axi_join | A connector that joins two AXI interfaces. | | | axi_lfsr | AXI4-attached LFSR; read returns pseudo-random data, writes are compressed into a checksum. | | | axi_lite_demux | Demultiplexes an AXI4-Lite bus from one slave port to multiple master ports. | Doc | | axi_lite_dw_converter | A data width converter between two AXI-Lite busses | [Doc][doc.axi_lite_dw_converter] | | axi_lite_from_mem | This module acts like an SRAM and makes AXI4-Lite requests downstream. | | | axi_lite_join | A connector that joins two AXI-Lite interfaces. | | | axi_lite_lfsr | AXI4-Lite-attached LFSR; read returns pseudo-random data, writes are compressed into a checksum. | | | axi_lite_mailbox | A AXI4-Lite Mailbox with two slave ports and usage triggered irq. | Doc | | axi_lite_mux | Multiplexes AXI4-Lite slave ports down to one master port. | Doc | | axi_lite_regs | AXI4-Lite registers with optional read-only and protection features. | [Doc][doc.axi_lite_regs] | | axi_lite_to_apb | AXI4-Lite to APB4 protocol converter.