230 skills found · Page 1 of 8
The-OpenROAD-Project / OpenLaneOpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
chili-chips-ba / Wireguard FpgaFull-throttle, wire-speed hardware implementation of Wireguard VPN, using low-cost Artix7 FPGA with opensource toolchain. If you seek security and privacy, nothing is private in our codebase. Our door is wide open for backdoor scrutiny, be it related to RTL, embedded, build, bitstream or any other aspect of design and delivery package. Bujrum!
4xmen / Web Package RTL⚡ Full RTL Package - Bootstrap Responsive Components For Iranian's 🇮🇷
Ali-Azmoud / Flutter XliderA material design slider and range slider with rtl support and lots of options and customization for flutter
IBM / AccDNNA compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
pulp-platform / CheshireA minimal Linux-capable 64-bit RISC-V SoC built around CVA6
chipsalliance / DromajoRISC-V RV64GC emulator designed for RTL co-simulation
pulp-platform / CrocA PULP SoC for education, easy to understand and extend with a full flow for a physical design.
4xmen / X Mega Menux mega menu is repsonsive mega menu based on vannilajs
hkust-zhiyao / RTLLMAn open-source benchmark for generating design RTL with natural language
F1ATB / Remote SDRRemote control of 2 Software Design Radio. Receiver and transmitter. Based on Adalm-Pluto SDR or RTL-SDR or Hack RF SDR or SDRplay and signal processing using GNU Radio on Raspberry PI. GUI on a web browser.
kunalg123 / VsdflowVSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
agalimberti / NoCRouterRTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
akilm / Physical DesignPhysical Design Flow from RTL to GDS using Opensource tools.
microdynamics-cpu / Tree Core IdeThe next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.
ekb0412 / 100DaysofRTL"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
abdelazeem201 / Cadence RTL To GDSII FlowIn this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.
4xmen / X Tree SelectTree Select jQuery plugin
mirseo / JSiliconJSilicon: A dual-mode 8-bit CPU core designed entirely from scratch by an AI major during mandatory military service in South Korea. This open-source Verilog project proves that real silicon design — from ALU to CPU architecture — is possible even under the most extreme constraints.
Essenceia / Nasdaq HFT FPGARTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
