VSDBabySoC

VSDBabySoC is a small SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.

Table of Contents

• Introduction to the VSDBabySoC
  • Problem statement
  • What is SoC
  • What is RVMYTH
  • What is PLL
  • What is DAC
• VSDBabySoC Modeling
  • RVMYTH modeling
  • PLL and DAC modeling
  • Step by step modeling walkthrough
• OpenLANE
  • OpenLANE installation
• Post-synthesis simulation
  • Synthesizing using Yosys
  • How to synthesize the design
  • Post-synthesis simulation (GLS)
  • Yosys final report
  • Static timing analysis using OpenSTA
    • Static timing analysis on the design
• VSDBabySoC Physical Design
  • OpenLANE details and flow
  • Other required tools
    • Magic
  • RVMYTH RTL2GDSII flow
    • RVMYTH layout generation setting up the environment
    • RVMYTH layout generation flow configuration
    • RVMYTH layout generation flow running
    • RVMYTH post-routing STA
    • RVMYTH post-routing simulation
    • RVMYTH final GDSII layout
  • VSDBabySoC-a mixed-signal RTL2GDSII flow
    • Prerequisites for mixed-signal implementation
      • LIB file and its usage
      • GDS file and its usage
      • LEF file and its usage
      • AVSDDAC-a ditital to analog converter
        • AVSDDAC getting the IP core
        • AVSDDAC preparing the LIB file
        • AVSDDAC preparing the GDS file
        • AVSDDAC preparing the LEF file
      • AVSDPLL-a phase-locked-loop
        • AVSDPLL Getting the IP core
        • AVSDPLL Preparing the LIB file
        • AVSDPLL Preparing the GDS file
        • AVSDPLL Preparing the LEF file
    • VSDBabySoC layout generation flow configuration
      • Creating proper SDC file
      • Floorplanning and placement configurations
    • VSDBabySoC layout generation flow running
    • VSDBabySoC post-routing STA
    • VSDBabySoC final GDSII layout
• Future works
• Contributors
• Acknowledgements

Introduction to the VSDBabySoC

VSDBabySoC is a small yet powerful RISCV-based SoC. The main purpose of designing such a small SoC is to test three open-source IP cores together for the first time and calibrate the analog part of it. VSDBabySoC contains one RVMYTH microprocessor, an 8x-PLL to generate a stable clock, and a 10-bit DAC to communicate with other analog devices.

Problem statement

This work discusses the different aspects of designing a small SoC based on RVMYTH (a RISCV-based processor). This SoC will leverage a PLL as its clock generator and controller and a 10-bit DAC as a way to talk to the outside world. Other electrical devices with proper analog input like televisions, and mobile phones could manipulate DAC output and provide users with music sound or video frames. At the end of the day, it is possible to use this small fully open-source and well-documented SoC which has been fabricated under Sky130 technology, for educational purposes.

What is SoC

An SoC is a single-die chip that has some different IP cores on it. These IPs could vary from microprocessors (completely digital) to 5G broadband modems (completely analog).

What is RVMYTH

RVMYTH core is a simple RISCV-based CPU, introduced in a workshop by RedwoodEDA and VSD. During a 5-day workshop students (including middle-schoolers) managed to create a processor from scratch. The workshop used the TLV for faster development. All of the present and future contributions to the IP will be done by students and under open-source licenses.

What is PLL

A phase-locked loop or PLL is a control system that generates an output signal whose phase is related to the phase of an input signal. PLLs are widely used for synchronization purposes, including clock generation and distribution.

What is DAC

A digital-to-analog converter or DAC is a system that converts a digital signal into an analog signal. DACs are widely used in modern communication systems enabling the generation of digitally-defined transmission signals. As a result, high-speed DACs are used for mobile communications and ultra-high-speed DACs are employed in optical communications systems.

VSDBabySoC Modeling

Here we are going to model and simulate the VSDBabySoC using iverilog, then we will show the results using gtkwave tool. Some initial input signals will be fed into vsdbabysoc module that make the pll start generating the proper CLK for the circuit. The clock signal will make the rvmyth to execute instructions in its imem. As a result the register r17 will be filled with some values cycle by cycle. These values are used by dac core to provide the final output signal named OUT. So we have 3 main elements (IP cores) and a wrapper as an SoC and of-course there would be also a testbench module out there.

Please note that in the following sections we will mention some repos that we used to model the SoC. However the main source code is resided in Source-Code Directory and these modules are in Modules Sub-Directory.

RVMYTH modeling

As we mentioned in What is RVMYTH section, RVMYTH is designed and created by the TL-Verilog language. So we need a way for compile and trasform it to the Verilog language and use the result in our SoC. Here the sandpiper-saas could help us do the job.

Here is the repo we used as a reference to model the RVMYTH

PLL and DAC modeling

It is not possible to sythesis an analog design with Verilog, yet. But there is a chance to simulate it using real datatype. We will use the following repositories to model the PLL and DAC cores:

1. Here is the repo we used as a reference to model the PLL
2. Here is the repo we used as a reference to model the DAC

CAUTION: In the beginning of the project, we get our verilog model of the PLL from here. However, by proceeding the project to the physical design flow we realize that this model needs a little changes to become sufficient for a real IP core. So we changed it a little and created a new model named AVSDPLL based on this IP

Step by step modeling walkthrough

In this section we will walk through the whole process of modeling the VSDBabySoC in details. We will increase/decrease the digital output value and feed it to the DAC model so we can watch the changes on the SoC output. Please, note that the following commands are tested on the Ubuntu Bionic (18.04.5) platform and no other OSes.

1. First we need to install some important packages:

$ sudo apt install make python python3 python3-pip git iverilog gtkwave docker.io
$ sudo chmod 666 /var/run/docker.sock
$ cd ~
$ pip3 install pyyaml click sandpiper-saas

2. Now we can clone this repository in an arbitrary directory (we'll choose home directory here):

$ cd ~
$ git clone https://github.com/manili/VSDBabySoC.git

3. It's time to make the pre_synth_sim.vcd:

$ cd VSDBabySoC
$ make pre_synth_sim

The result of the simulation (i.e. pre_synth_sim.vcd) will be stored in the output/pre_synth_sim directory.

4. We can see the waveforms by following command:

$ gtkwave output/pre_synth_sim/pre_synth_sim.vcd

Two most important signals are CLK and OUT. The CLK signal is provided by the PLL and the OUT is the output of the DAC model. Here is the final result of the modeling process:

In this picture we can see the following signals:

• CLK: This is the input CLK signal of the RVMYTH core. This signal comes from the PLL, originally.
• reset: This is the input reset signal of the RVMYTH core. This signal comes from an external source, originally.
• OUT: This is the output OUT signal of the VSDBabySoC module. This signal comes from the DAC (due to simulation restrictions it behaves like a digital signal which is incorrect), originally.
• RV_TO_DAC[9:0]: This is the 10-bit output [9:0] OUT port of the RVMYTH core. This port comes from the RVMYTH register #17, originally.