12 skills found
rafaelcalcada / RvxRISC-V microcontroller IP core for embedded, FPGA and ASIC applications
AngeloJacobo / RISC VDesign implementation of the RV32I Core in Verilog HDL with Zicsr extension
SonalPinto / KronosKronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
qubeck78 / TangerineA7 200RiscV based SOC for Qmtech Artix A7-200 board. Includes nekoRv: RISC-V 32 IM Zicsr core. And yes, it runs DOOM :)
gaph-pucrs / RS5RV32I[M][A][C][V]Zicntr[_Zicond]_Zicsr_Zihpm[_Zcb][_Zkne][_Xosvm] processor
JN513 / Grande Risco 5Grande RISCO 5 is a RISC-V RV32IMBC_Zicsr processor with a 5-stage pipeline, developed in just a few days off.
VishankSingh / Riscv Simulator 2A RISCV64IMFD simulator supporting syscalls and zicsr extension. You might want to use the simulator with the vscode extension linked below.
wyvernSemi / Rv32An configurable open-source RISC-V instruction set simulator in C++. RV32GBC_Zicsr_Zbc_Zicntr.
Kingfish404 / Raptor ChipOoO 6-stage CPU (rv32imac_zicntr_zicsr_zifencei).
jesseopdenbrouw / Thuas RiscvThe THUAS RISC-V RV32IM Zicsr Zicntr Zihpm Zicond Zimop Zba Zbb Zbs Sdext Sdtrig microcontroller
LockBlock-dev / VectorRISC-V ISA emulator
JohnH2448 / Anvil DemoRISC-V 5-Stage M-Mode RV32I Zicsr Core in SystemVerilog
