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Xilinx / Vitis AIVitis AI is Xilinx’s development stack for AI inference on Xilinx hardware platforms, including both edge devices and Alveo cards.
Xilinx / Vitis TutorialsVitis In-Depth Tutorials
Xilinx / Vitis LibrariesVitis Libraries
Xilinx / Vitis HLS Introductory ExamplesNo description available
Xilinx / XRTRun Time for AIE and FPGA based platforms
Xilinx / Vitis Accel ExamplesVitis_Accel_Examples
Xilinx / Vitis AI TutorialsNo description available
Xilinx / HLSVitis HLS LLVM source code and examples
pavel-demin / Red Pitaya NotesNotes on the Red Pitaya Open Source Instrument
definelicht / HlslibA collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
fpgasystems / Vitis With 100Gbps TCP IP100 Gbps TCP/IP stack for Vitis shells
Xilinx / Finn HlslibVitis HLS Library for FINN
Xilinx / Xup Vitis Network ExampleVNx: Vitis Network Examples
Xilinx / Vitis Embedded Platform SourceNo description available
triSYCL / SyclSYCL for Vitis: Experimental fusion of triSYCL with Intel SYCL oneAPI DPC++ up-streaming effort into Clang/LLVM
Xilinx / Vitis Model ComposerVitis Model Composer Examples and Tutorials
metr0jw / Event Driven Spiking Neural Network Accelerator For FPGAEnergy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration
Xilinx / Vitis In Depth TutorialNo description available
Xilinx / Kria Vitis PlatformsKria Vitis platforms and overlays
gewuek / Vitis AI Custom Platform FlowThis project is trying to create a base vitis platform to run with DPU
