26 skills found
SystemRDL / Systemrdl CompilerSystemRDL 2.0 language compiler front-end
Juniper / Open Register Design ToolTool to generate register RTL, models, and docs using SystemRDL or JSpec input
SystemRDL / PeakRDL RegblockGenerate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
zhajio1988 / Open RegModel:hatched_chick:Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
SystemRDL / PeakRDL HtmlGenerate address space documentation HTML from compiled SystemRDL input
SystemRDL / PeakRDL UvmGenerate UVM register model from compiled SystemRDL input
HEP-SoC / PeakRDL HalcppC++ 17 Hardware abstraction layer generator from systemrdl
hughjackson / PeakRDL VerilogGenerate verilog register file from systemRDL description
krcb197 / PeakRDL PythonGenerate Python Register Access Layer (RAL) from SystemRDL
OpenHisiIpCam / Registers DescriptionHiSilicon ip camera SoCs SystemRDL registers description
Minres / RDL EditorA Xtext based SystemRDL editor with syntax highlighting and context sensitive help
SystemRDL / Tree Sitter SystemrdlSystemRDL grammar for tree-sitter
MicroTCA-Tech-Lab / HectareVHDL generator from SystemRDL
robinkjoy / Systemrdl CompilerTool to generate synthesizable RTL files from SystemRDL input
SimplHDL / SimplhdlSimulation and implementation flow for hardware description languages
SystemRDL / Vscode SystemrdlSystemRDL language support for VS Code
HEP-SoC / PeakRDL OpentitanSystemRDL <-> Opentitan regtool hjson format exporter, importer
NuQuantum / Peakrdl SvA SystemRDL exporter for SystemVerilog
Silicon1602 / Srdl2svA SystemRDL 2.0 to (synthesizable) SystemVerilog compiler.
OpenHisiIpCam / Hisi Initregtable Go ParserHiSilicon SoC`s U-Boot initial register table parser into human readable format
