11 skills found
basemhesham / Design And ASIC Implementation Of UARTThis repository presents ASIC design flow for UART utilizing RTL to GDS implementation This has been simulated on VCS and has been implemented by using Verilog description language which has been synthesized using Design Compiler and Back End design using Synopsys IC Compiler II
jomonkjoy / Tool Make ScriptSynopsys Design compiler, VCS and Tetra-MAX
ehao222 / ASIC Design Example RISC CPUBase on Synopsys platform using VCS,DC,ICC,PT.
ameyjain / VERILOG RootMeanSquareCalculatorRMSC with operating frequency of 300MHz. Coded, simulated and synthesized on Verilog RTL 72 stages Pipelining of division and square root block producing the result using a synchronous FIFO. Tools and Languages: Synopsys VCS, Synopsys Design Vision, GTK Wave, NC-Verilog, Verilog HDL
tatan432 / AES ENCODERRTL implementation for Advanced Encryption Standard (AES) in Verilog. Synthesis Done in Synopsys DC.
Divyesh945 / AXI VIP VerificationVerification environment for the AXI protocol, focusing on AXI4 functionality. Includes a UVM-based testbench designed to validate protocol compliance across various transfer scenarios. Emphasizes functional coverage and debugging, using SystemVerilog and Synopsys VCS to ensure robust protocol verification.
SimplHDL / SimplhdlSimulation and implementation flow for hardware description languages
dongremayur777 / 28T Full Adder Using 28nm CMOS Technology28T Full Adder Design made using Synopsys VCS Tool for VSD organized IIT Hyderabad Hackathon.
RUC-Turing / Docker SynopsysRun Synopsys VCS in Docker, for ALL users on a shared server.
vb000 / Vcs Slave ModeExample to control VCS simulation with a C/C++ program. This involves VCS output a shared object instead of an executable (simv).
ds18nomad / NN Calculator SOC DesignDesigned a SOC with the hardware capability of a Neural Network calculator which used to communicate with two different memories, one of which was for fetching weights and inputs to the calculator and other was to store the output result after the multiplication and summation. - The design was divided into three pipelined modules to achieve high performance and reduce latency. - The design was on implemented on 5 master/slave AHB bus model to control the flow of inputs,weights and outputs of neural network calculator. - Major involvement in synthesis and static time analysis. - EDA Tool: Synopsys VCS, Language: SystemVerilog.
