4 skills found
vertexclique / KovanHigh-performance wait-free memory reclamation for wait-free data structures (ASMR). Bounded memory usage, predictable latency.
digitarald / Loop AgentLoop: A meta-loop orchestrator for multi-agent Copilot workflows with self-correction, stall detection, and shared memory
ian-chuang / Gazebo Gripper Action ControllerA ROS control gripper action controller designed for Gazebo simulation environments. Enhances the functionality of the original ros_controllers repository with improved stalling detection mechanism and adjusted behavior for successful actions during stalling.
akankshac-073 / MIPS 5 Stage Pipelined Control And DatapathImplementation of a 32-bit 5 stage Pipelined MIPS Processor using RTL coding in Verilog on ModelSim simulator. The processor datapath and control units are designed for Arithmetic and Logical instructions (all r-type instructions + addi, andi, ori, slti), Data transfer instructions (lw, sw), Branch and jump instructions (beq, j). Forwarding control, hazard detection and stalling units are also implemented to improve the efficiency of the pipeline. The designed processor can be tested by initializing the instruction memory with test instructions and obtaining the corresponding register contents by generating waveforms on ModelSim.
