106 skills found · Page 1 of 4
davidepatti / NoximNetwork on Chip Simulator
pulp-platform / FlooNoCA Fast, Low-Overhead On-chip Network
ucb-bar / ConstellationA Chisel RTL generator for network-on-chip interconnects
taichi-ishitani / TnocNetwork on Chip Implementation written in SytemVerilog
aignacio / RavenocRaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
neurosim / DNN NeuroSim V2.1Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
karthisugumar / CSE240D Hierarchical Mesh NoC Eyeriss V2A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Accelerator
LBL-CoDEx / OpenSoCFabricOpenSoC Fabric - A Network-On-Chip Generator
agalimberti / NoCRouterRTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
XUANTIE-RV / Csi Nn2An optimized neural network operator library for chips base on Xuantie CPU.
anan-cn / Open Source Network On Chip Router RTLNo description available
bakhshalipour / NoC VerilogA verilog implementation for Network-on-Chip
matutani / NocgenNoC (Network-on-Chip) generator that generates Verilog HDL model of NoC consisting of on-chip routers
smartboxchannel / EFEKTA THPIt is a wireless temperature, pressure and humidity sensor, supports working in Zigbee networks. (Zigbee2mqtt open source project). Built on CC2530 chip (Zigbee), two modications: Ebyte E18-MS1PA2-PCB radio module with amplifier and Ebyte E18-MS1-PCB. Powered by the most common AAA batteries.
amonemi / ProNoCPrototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
neurosim / DNN NeuroSim V2.0Benchmark framework of compute-in-memory based accelerators for deep neural network (on-chip training chip focused)
cornell-brg / Pymtl3 NetProject repo for the POSH on-chip network generator
ic-lab-duth / NoCpadHLS for Networks-on-Chip
andrewboutros / Rad FlowThe RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration devices (RADs). These devices incorporate conventional FPGA fabrics, several coarse-grained domain-specialized accelerator blocks, and high-performance networks-on-chip for system-level communication.
KyleParkJong / Network On Chip SimulatorNetwork on-Chip (NoC) simulator for simulating intra-chip data flow in Neural Network Accelerator
