192 skills found · Page 1 of 7
emsec / HalHAL – The Hardware Analyzer
nturley / Netlistsvgdraws an SVG schematic from a JSON netlist
OSCC-Project / IEDAAn open-source EDA infrastructure and tools from netlist to GDS
StefanSchippers / XschemA schematic editor for VLSI/Asic/Analog custom designs, netlist backends for VHDL, Spice and Verilog. The tool is focused on hierarchy and parametric designs, to maximize circuit reuse.
mist64 / Perfect6502perfect6502, a MOS 6502 CPU emulator that performs a simulation of the original NMOS 6502 netlist
SiEPIC / SiEPIC ToolsPackage for KLayout to add integrated optics / silicon photonics functionality (waveguides, netlist extraction, circuit simulations, etc)
google / PcbdlPCB Design Language: A programming way to design schematics.
gdevic / Z80ExplorerVisual Zilog Z80 netlist-level simulator
kunalg123 / VsdflowVSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft their ideas in RTL language, and convert the design to hardware using VSD (RTL-to-GDS) FLOW. VSDFLOW is completely build using OPHW tools, where the user gives input RTL in verilog. From here on the VSDFLOW takes control, RTL is synthesized (using Yosys). The synthesized netlist is given to PNR tool (Qflow) and finally Sign-off is done with STA tool (using Opentimer). The output of the flow is GDSII layout and performance & area metrics of your design. VSDFLOW also provide hooks at all stages for users working at different levels of design flow. It is tested for 30k instance count design like ARM Cortex-M0, and can be further tested for multi-million instance count using hierarchical or glue logic.
najaeda / NajaStructural Netlist API (and more) for EDA post synthesis flow development
RTimothyEdwards / NetgenNetgen complete LVS tool for comparing SPICE or verilog netlists
circuitgraph / CircuitgraphTools for working with circuits as graphs in python
pmonta / FPGA Netlist ToolsTools for emulating transistor-level netlists on FPGAs
byuccl / SpydrnetA flexible framework for analyzing and transforming FPGA netlists. Official repository.
stnolting / Neorv32 Verilog♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
f18m / Netlist ViewerSPICE netlist visualizer
VenciFreeman / FFT ChipDesignA 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
thadeuluiz / RTspiceA real-time netlist based audio circuit plugin
galacticstudios / KiCadVerilogGenerate Verilog code from a KiCad netlist
aaanthonyyy / CircuitNetA hand-drawn schematic sketch recognizer and converter. Three-Step pipeline: Component detection using traditional image processing; Component classification using a custom trained CNN; Schematic generation using a proprietary generation algorithm.
