80 skills found · Page 1 of 3
ghdl / GhdlVHDL 2008/93/87 simulator
olofk / EdalizeAn abstraction library for interfacing EDA tools
ghdl / Ghdl Yosys PluginVHDL synthesis (based on ghdl)
suoto / Hdl CheckerRepurposing existing HDL tools to help writing better code
jakubcabal / Spi FpgaSPI master and SPI slave for FPGA written in VHDL
PyFPGA / PyfpgaA Python package to use FPGA development tools programmatically.
wyvernSemi / PcievhostPCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities
jakubcabal / Uart For FpgaSimple UART controller for FPGA written in VHDL
ghdl / Ghdl Language ServerLanguage server based on ghdl
stnolting / Neorv32 Verilog♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
stnolting / Neorv32 Setups📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.
Paebbels / JSON For VHDLA JSON library implemented in VHDL.
tmeissner / Psl With GhdlExamples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
yaonyan / GhdlA much more convenient way to download GitHub release binaries on the command line, works on Win & Unix-like systems
ghdl / Ghdl CosimDocumentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
mnemocron / My Discrete FpgaMy own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
ghdl / DockerScripts to build and use docker images including GHDL
tmeissner / Formal Hw VerificationTrying to verify Verilog/VHDL designs with formal methods and tools
dbhi / VboardVirtual development board for HDL design
tmeissner / Cryptocorescryptography ip-cores in vhdl / verilog
