178 skills found · Page 1 of 6
doonny / PipeCNNAn OpenCL-based FPGA Accelerator for Convolutional Neural Networks
JulianKemmerer / PipelineCA C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.
zssloth / Embedded Neural Networkcollection of works aiming at reducing model sizes or the ASIC/FPGA accelerator for machine learning
quanzaihh / Neural Network AcceleratorA Convolutional Neural Network Accelerator implementation on FPGA, xilinx （xczu7ev-ffvc1156-2-i）, The inference of yolov8 took 60ms.
sjtu-zhao-lab / PomAn Optimizing Framework on MLIR for Efficient FPGA-based Accelerator Generation
IBM / AccDNNA compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
LeiWang1999 / ZYNQ NVDLANVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.
changwoolee / Lenet5 HlsFPGA Accelerator for CNN using Vivado HLS
Xilinx / Finn ExamplesDataflow QNN inference accelerator examples on FPGAs
lirui-shanghaitech / CNN Accelerator VLSIConvolutional accelerator kernel, target ASIC & FPGA
abs-tudelft / FletcherFletcher: A framework to integrate FPGA accelerators with Apache Arrow
xjtuiair-cag / XJTU TriplerXJTU-Tripler is based on HiPU100, an FPGA-friendly DNN accelerator, developed by CAG, Institute of AI & Robotics, XJTU.
UCLA-VAST / TapaTAPA compiles task-parallel HLS program into high-performance FPGA accelerators. UCLA-maintained.
thedatabusdotio / Fpga Ml AcceleratorThis repository hosts the code for an FPGA based accelerator for convolutional neural networks
cea-wind / SimpleTPUA FPGA Based CNN accelerator, following Google's TPU V1.
gnodipac886 / ViT FPGA TPUFPGA based Vision Transformer accelerator (Harvard CS205)
hguq / HG PIPEFPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
metr0jw / Event Driven Spiking Neural Network Accelerator For FPGAEnergy-efficient Event-driven Spiking Neural Network accelerator for FPGA with PyTorch integration
pp-Innovate / FPGA ZynqNetFPGA-based ZynqNet CNN accelerator developed by Vivado_HLS
StefanSredojevic / Deep Neural Network Hardware AcceleratorSystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK Software
