26 skills found
chipsalliance / OmnixtendOmniXtend cache coherence protocol
pulp-platform / CulsansTightly-coupled cache coherence unit for CVA6 using the ACE protocol
trigonak / Ssmpssmp is a highly optimized message-passing library built on top of the cache-coherence protocols of shared memory processors.
Errare-humanum-est / HeteroGenWe solve the two challenges architects face when designing heterogeneous processors with cache coherent shared memory. First, we develop an automated tool, called HeteroGen, for composing clusters of cores, each with its own coherence protocol. Second, we show that the output of HeteroGen adheres to a precisely defined memory consistency model that we call a compound consistency model. For a wide variety of protocols --- including the MOESI variants, as well as those that are targeted towards Total Store Order and Release Consistency --- we show that HeteroGen can correctly fuse them. To validate HeteroGen, we develop the first litmus tests for verifying that heterogeneous protocols satisfy compound consistency models. To understand the possible performance implications of automatic protocol generation, we compared against a publicly available manually-generated heterogeneous protocol. Our results show that performance is comparable.
Errare-humanum-est / ProtoGenDesigning directory cache coherence protocols is complicated because coherence transactions are not atomic in modern multicore processors. A coherence transaction comprises multiple messages, and these messages can interleave with other conflicting coherence transactions initiated by other cores. To overcome this architectural challenge, we present ProtoGen, an automated tool for taking the description of a directory protocol with atomic transactions (i.e., no concurrency) and generating the corresponding protocol for a multicore with non-atomic transactions. ProtoGen outputs the finite state machines for the cache and directory controllers, including all of the transient states that are possible with concurrent transactions. We have used ProtoGen to generate complete MSI, MESI, and MOSI protocols given their stable state protocol specifications. We have verified the generated protocols for safety and deadlock freedom using the Murϕ model checker. Our generated protocols are identical to or better than manually generated protocols, at times even discovering opportunities to reduce stalling.
Lancern / Cache Coherence Protocol BenchBenchmarking code for evaluating the cost of cache coherence protocols implemented on different platforms
mit-plv / HemiolaA Coq framework to support structural design and proof of hardware cache-coherence protocols
marcotulio956 / Cache.coherencyLAOCIIExerting coherency between caches with protocols in a Memory-Shared Multiprocessors system whether it has uniform memory access(UMA, symmetric) or not(non-UMA).
midn8hustlr / MSI Cache CoherenceImplementing a snoopy cache coherence for dual core processor with MSI protocol using Verilog HDL
theoxo / CoherenceMSI cache coherence protocol written/verified in Murphi
wshenyi / EECS570 HW2 MOESIFive-state 3-hop MOESI Cache Coherence Protocol Implemented in Murphi
quantumquantara-arch / Lumeren LanguageA formal, minimal implementation of the Luméren language — a 22-glyph coherence protocol for interintelligence communication. Includes lexicon, κ-space scoring, and a text→glyph demo.
Ghonimo / Design And Simulation Of Split L1 Cache PSU ECE585An in-depth project focusing on the design and simulation of a split L1 cache in C++. This repository covers MESI protocol operations, comprehensive test cases, and simulation results, showcasing strategies for enhancing cache coherence and performance. This is a class project from ECE 585: Microprocessor System Design at Portland State University
zzhu35 / Spandex CachesHardware Caches for Spandex Coherence Protocol
ashithav / CacheImplement cache coherence protocols: MSI, MESI and Dragon.
adamozh / Cache Coherence SimulatorA cache coherence simulator for MESI, MOESI and Dragon Protocols.
Yefei100 / Cache Coherence ProtocolA C++ implementation of cache coherence protocol, including MSI, MESI and Dragon.
ease-lab / 1UpdateThis repository contains the TLA+ specification of the 1-Update cache coherence protocol that appeared in PACT'21.
adityagupta1089 / Cache Coherence SimultaorSimulator that simulates multiprocessor caches and involved cache coherence protocols
7ossamfarid / MCP MindmeshClaude 3.7 Swarm with Field Coherence: A Model Context Protocol (MCP) server that orchestrates multiple specialized Claude 3.7 Sonnet instances in a quantum-inspired swarm. It creates a field coherence effect across pattern recognition, information theory, and reasoning specialists to produce optimally coherent responses from ensemble intelligence.
