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B-Lang-org / BscBluespec Compiler (BSC)
WangXuan95 / BSV Tutorial Cn一篇全面的 Bluespec SystemVerilog (BSV) 中文教程，介绍了BSV的调度、FIFO数据流、多态等高级特性，展示了BSV相比于传统Verilog开发的优势。
sifive / KamiKami - a DSL for designing Hardware in Coq, and the associated semantics and theorems for proving its correctness. Kami is inspired by Bluespec. It is actually a complete rewrite of an older version from MIT
cambridgehackers / ConnectalConnectal is a framework for software-driven hardware development.
mit-plv / KamiA Platform for High-Level Parametric Hardware Specification and its Modular Verification
rsnikhil / Bluespec BSV TutorialBluespec BSV HLHDL tutorial
oxidecomputer / CobaltA collection of common Bluespec interfaces/modules.
rsnikhil / Learn Bluespec And RISCV DesignTextbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
p4fpga / P4fpgaP4-14/16 Bluespec Compiler
sangwoojun / BluespecpciePCIe library for the Xilinx 7 series FPGAs in the Bluespec language
rsnikhil / ICFP2020 Bluespec TutorialTutorial on hardware design using Bluespec BH (Bluespec Classic) for Haskell programmers at ACM ICFP 2020 conference
kcamenzind / BluespecIntroGuideAn introductory guide to Bluespec (BSV)
CTSRD-CHERI / BluecheckA generic test bench written in Bluespec
datenlord / Blue RdmaRoCEv2 hardware implementation in Bluespec SystemVerilog
hyoukjun / DesignCNNAcceleratorsLab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
adamgallas / MIT Bluespec RISCV TutorialNo description available
thotypous / AlterajtaguartAltera JTAG UART wrapper for Bluespec
CTSRD-CHERI / RVBSRISC-V BSV Specification
rsnikhil / RISCV ISA Formal Spec In BSVA formal spec of the RISC-V Instruction Set Architecture, written in Bluespec BSV (executable, synthesizable)
chipsalliance / OmnixtendEndpointHardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.
