33 skills found · Page 1 of 2
OSVVM / AXI4AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream transmitter and receiver verification components
mmxsrup / Axi4 InterfaceAXI4 and AXI4-Lite interface definitions
2cc2ic / Motion Detection System Based On Background ReconstructionThis work is based on PYNQ-Z2 development board provided by organizer, and adopts the cooperation scheme of hardware and software to build a DMA based image data cache transmission system. On this basis, Verilog HDL was used to design the axi4-stream interface based IP core for image processing, so as to build a high real-time moving target detection system. In our design, we focus on the optimization of processing pipeline, improve the traditional frame difference method, and achieve the optimization goal of saving logical resources through the accumulation compression and reconstruction expansion of cached background frames.
VHDL / InterfacesInterface definitions for VHDL-2019.
Aperture-Electronic / Realtime Bicubic 16X SuperResolution IPAPV21B - Real-time Video 16X Bicubic Super-resolution IP, AXI4-Stream Video Interface Compatible, 4K 60FPS
absolutezero2730 / AXI DMA FIFOTransfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA
suisuisi / AXI4 Stream FIR FilterAXI4-Stream FIR filter IP
hpcn-uam / Efficient Checksum Offload EngineChecksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream interface.
corna / Cocotbext Axi4streamNo description available
nhynes / Chisel3 AxiChisel3 AXI4-{Lite, Full, Stream} Definitions
makararasi / UVM AXI4 StreamNo description available
dylanmsu / BT656 To AXI4SVHDL sources for a BT.656 to axi4-stream converter
taitashaw / HLS FPGA🚀 Real-Time High-Level Synthesis (HLS) Projects for UltraScale+ FPGAs. Accelerated design pipelines, dataflow architectures, and low-latency compute cores — powered by Vitis HLS, AXI4-Stream, and signal processing for 5G, SDR, and HFT applications. 🔧🔬💡
lucasbrasilino / Axis Exec OpVerilog module for executing logic operations over AXI4-Stream interface data.
sthornington / Gemmm2sVerilog module for converting from AXI4 MM of Zynq GEM Ethernet DMA to AXI-Stream with packet boundaries
xiaochuang-lxc / AMBA SVAARM AMBA 4 AXI4,AXI4-lite,AXI4-stream SVAs (BP063) MiscellaneousBP063
helix-osu-firmware / Axi Ethernet StreamerEthernet to AXI4-Stream using UDP/IP
QianfengClarkShen / Lbus Axis ConverterLbus to AXI4-Stream converter in verilog
tanerguven / StreamIFThis project is part of my master's thesis. Source code shared for the publication "StreamIF - AXI4 Memory Mapped to AXI4 Stream Interface Library"
paulscherrerinstitute / VivadoIP Axi Mm ReaderRead AXI4-MM registers regularly with exact timing and provide them as AXI4-Stream or in a FIFO to be read by SW
