72 skills found · Page 1 of 3
alexforencich / Verilog AxisVerilog AXI stream components for FPGA implementation
fpganinja / TaxiAXI, AXI stream, Ethernet, and PCIe components in System Verilog
ultraembedded / Core JpegHigh throughput JPEG decoder in Verilog for FPGA
KastnerRG / Cgra4mlAn Open Workflow to Build Custom SoCs and run Deep Models at the Edge
alknvl / Axis UdpThis repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supported. The project was tested on Xilinx 7-series FPGA with 10G Ethernet MAC IP-core
jacobfeder / AxisfifoZynq SoC Linux kernel driver for Xilinx AXI-Stream FIFO IP
andrewstart / Axios StreamingExample of using axios to get a request, and streaming the result.
Aperture-Electronic / SystemVerilog Bitmap Library AXI Image VIPBitmap Processing Library & AXI-Stream Video Image VIP
alexforencich / Verilog Ft245Verilog FT245 to AXI stream interface
catkira / DDSHDL code for a DDS (direct digital synthesizer) with AXI stream interface
lucasbrasilino / Net2axisVerilog network module. Models network traffic from pcap to AXI-Stream
absolutezero2730 / AXI DMA FIFOTransfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA
DOUDIU / Video Stitching On FPGAThis open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.
shariethernet / RPHAXRPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has support for AXI-Stream IP with Single Master and Single Slave Template. The user can code the Hardware Accelerator in TL-Verilog/Verilog/System Verilog and use this flow to automatically package into an IP and create a Zynq based block design.
suisuisi / AXI4 Stream FIR FilterAXI4-Stream FIR filter IP
anthonyeden / Axia Livewire Stream Address HelperPython helper methods for Axia Livewire Audio-Over-IP Multicast Addresses.
fcayci / Vhdl Axis UartUART to AXI Stream interface written in VHDL
corna / Cocotbext Axi4streamNo description available
e1ioan / RaspberryPi AxisYoutubeStreamingStream live video to youtube using a RaspberryPi and an Axis IP camera
catkira / CICHDL code for a complex multiplier with AXI stream interface
