25 skills found
UVVM / UVVMUVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of FPGA and ASIC – resulting also in significant quality improvement. Community forum: https://forum.uvvm.org/ UVVM.org: https://uvvm.org/
troyguo / Awesome DvAwesome ASIC design verification
abdelazeem201 / Systolic Array Implementation In RTL For TPUIC implementation of Systolic Array for TPU
kumarrishav14 / AXIVIP for AXI Protocol
wyvernSemi / VprocVirtual processor co-simulation element for Verilog, VHDL and SystemVerilog environments, allowing host compiled programs to run in a logic simulation. and drive a memory mapped bus
abdelazeem201 / Design And ASIC Implementation Of 32 Point FFT ProcessorI present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
WilliamZhang20 / ECE298A TPUA custom AI chip to be taped out soon!
10x-Engineers / Infinite ISP ReferenceModelA Python based fixed-point implementation of the Infinite-ISP design for ASIC and FPGA design and verification.
Lampro-Mellon / QuasarQuasar 2.0: Chisel equivalent of SweRV-EL2
fvmformal / FvmA Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (this is a mirror of https://gitlab.com/fvmformal/fvm : you can open issues there)
edgarsj / EdocviewerView and verify EU standard ASiC-E and Latvian eDoc files. PWA app
zli87 / Wishbone To I2C Bus Controller IP VerificationASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.
nicolavianello95 / RISC VDesign, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.
m-kru / Go HdlHdl is a tool for easing the work with hardware description languages.
abdelazeem201 / LEON2The LEON2 is a synthesisable VHDL model of a 32-bit processor conforming to the IEEE-1754 (SPARC V8) architecture.
shaoxq1205 / LC3 VerificationASIC Verification Project
SalomeDevkule7 / Neural Network Layer GeneratorApplication Specific Integrated Circuit(ASIC)
Siddharthc8 / ASIC Design And VerificationThis repository contains a collection of Verilog and SystemVerilog design files, along with their respective testbenches. It also includes UVM (Universal Verification Methodology) testbenches for advanced verification needs.
HimmelAward / PoTEVThis decentralized blockchain integrates differential geometry, using unique high-dimensional manifold embeddings (non-self-intersecting with curvature bounds) as ASIC-resistant proof-of-work, creating a novel consensus mechanism based on mathematical topology verification.
kumarrishav14 / I2CVIP for I2C
