120 skills found · Page 1 of 4
hughperkins / VeriGPUOpenSource GPU, in Verilog, loosely based on RISC-V ISA
chipsalliance / Cores VeeR EH1VeeR EH1 core
google / QkerasQKeras: a quantization deep learning library for Tensorflow Keras
abdelazeem201 / ASIC Design RoadmapThe journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a concept to specification to tape-outs. Although the end product is typically quite small (measured in nanometers), this long journey is interesting and filled with many engineering challenges.
dpretet / Async FifoA dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
librelane / LibrelaneASIC implementation flow infrastructure, successor to OpenLane
troyguo / Awesome DvAwesome ASIC design verification
abdelazeem201 / Systolic Array Implementation In RTL For TPUIC implementation of Systolic Array for TPU
chipsalliance / Cores VeeR EL2VeeR EL2 Core
lirui-shanghaitech / CNN Accelerator VLSIConvolutional accelerator kernel, target ASIC & FPGA
dpretet / Axi CrossbarAn AXI4 crossbar implementation in SystemVerilog
mflowgen / Freepdk 45nmASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
cpc / OpenasipOpen Application-Specific Instruction Set processor tools (OpenASIP)
thousrm / Universal NPU CNN Acceleratorhardware design of universal NPU(CNN accelerator) for various convolution neural network
AUCOHL / DFFRAMStandard Cell Library based Memory Compiler using FF/Latch cells
KastnerRG / Cgra4mlAn Open Workflow to Build Custom SoCs and run Deep Models at the Edge
efabless / Foss Asic ToolsFOSS-ASIC-TOOLS is all in one container for SKY130 based design both Analog and Digital. Below is a list of the current tools already installed and ready to use.
SkillSurf / SystemverilogSystemVerilog for ASIC/FPGA Design & Simulation, with Synopsys Tool Flow
JeffDeCola / My Verilog ExamplesA place to keep my synthesizable verilog examples.
abdelazeem201 / Design And ASIC Implementation Of 32 Point FFT ProcessorI present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
