388 skills found · Page 3 of 13
amaranth-lang / Rtl DebuggerVS Code based debugger for hardware designs in Amaranth or Verilog
EscapeTHU / SGBM FPGAThis repository contains code and pdf tutorial of how I've implemented binocular camera matching algorithm, SGBM, with FPGA using verilog. Code in this repo contains both C++ SGBM simulation code and PS-PL vitis-vivado project. Tutorial and the video attached thoroughly explain my designation in detail, although made in Chinese hhhhh.
MMujtabaRoohani / RISC V ProcessorA verilog based 5-stage pipelined RISC-V Processor code.
thu-cs-lab / Verilog Coding StandardRecommended coding standard of Verilog and SystemVerilog.
Renuga2004 / VLSI IMPLEMENTATION OF TURBO CODE FOR LTE USING VERILOG HDLNo description available
facebookresearch / VeripyVeriPy is a python based Verilog/Systemverilog automation tool. It automates ports/wire/reg/logic declarations, sub-module Instantiation, embedded python, IO spec flow, memory wrapper generation, various code generation plugins and configurable code generation. The VeriPy Wiki has more the detailed documentation.
EEESlab / Combinational BnnSystem Verilog code describing a fully combinational binarized neural network.
PRIYADHARSHINI-2930 / Turbo Code LTE Verilog HDLNo description available
jdocampom / JPEG DecoderVerilog Code for a JPEG Decoder
scale-lab / DRUMThe Verilog source code for DRUM approximate multiplier.
M-HHH / HDLBits Practice VerilogThis is a practice of verilog coding
norandomtechie / Ece270 SimulatorSource code for Web-Based Verilog Simulation Platform in ECE 27000 at Purdue University
lawrie / Verilog ExamplesExample code in Verilog for the Blackice II FPGA
hyoukjun / DesignCNNAcceleratorsLab code for three-day lecture, "Designing CNN Accelerators using Bluespec System Verilog", given at SNU in December 2017
chiphackers / CoveredCovered is a Verilog code coverage utility using VCD/LXT/FST dumpfiles (or VPI interface) and the design to generate line, toggle, memory, combinational logic, FSM state/arc and assertion coverage report metrics viewable via GUI or ASCII format.
tritechpw / Make FPGARepository of Verilog code for Make:FPGA book Chapters 2 & 3.
jonlwowski012 / OV7670 NEXYS4 VerilogThis code is used to connect the OV7670 Camera to a NEXYS4 and then display the image on a monitor in Verilog
aklsh / Getting Started With VerilogVerilog modules for beginners
DiabloBlood / Single Cycle MIPS CPUCourse project of Computer Architecture, designed by single-cycle datapath. The verilog code could be completely compiled by Quartus II.
sjj-star / Automatically Generate Wallace Tree VerilogHDL Code本工具用于自动生成一个Wallace Tree算法VerilogHDL代码实例，并附带了一些配套的工具和一个完整的VerilogHDL描述的乘法器。
