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Mreg

UVM register model course

Install / Use

/learn @verification-explorer/Mreg
About this skill

Quality Score

0/100

Supported Platforms

Universal

README

UVM register model course

This repository is associated with a course I completed on UVM register modeling (currently available only in Hebrew). The topics covered in the course include

  1. Introduction
  2. Register block structure
  3. Adapter
  4. Predictor
  5. Predictor Explicit-Implicit mode
  6. Adapter provides_response
  7. Built in sequences
  8. Register model APIs
  9. Hooks and callback introduction
  10. Hooks and callback bitwise and register example
  11. Hooks and callbacks status register example
  12. Hooks and callbacks ID register example
  13. Multiple maps
  14. Burst

Enjoy!

Recorded Course

View on GitHub
GitHub Stars5
CategoryDevelopment
Updated1y ago
Forks0

Languages

SystemVerilog

Security Score

70/100

Audited on May 8, 2024

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