FPAM
Combinational adder and multiplier modules for IEEE 754 single-precision and double-precision floating point format.
Install / Use
/learn @suoglu/FPAMREADME
Floating Point Adder Multiplier
Contents of Readme
- About
- Modules
- Interface Description
- Performance and Resource Utilization
- Simulation
- Test
- Status Information
- Issues
About
Work in Progress!
Fully combinational adder and multiplier modules for IEEE 754 single-precision (binary32) and double-precision (binary64) floating point format.
Modules
Two computation modules and a simple wrapper that contains both adder and multiplier.
Interface Description
Ports
Ports of the all modules/IPs named in same manner.
| Port | Type | Width | Occurrence | Description | Notes |
| :------: | :----: | :----: | :----: | :-----: | ---- |
| num0 | I | BIT_SIZE | Mandatory | Operand | |
| num1 | I | BIT_SIZE | Mandatory | Operand | |
| res | O | BIT_SIZE | Mandatory | Result | |
| overflow | O | 1 | Optional | Result is infinite / Overflowed | |
| zero | O | 1 | Optional | Result is zero | |
| NaN | O | 1 | Optional | At least one of the inputs are not a number | |
| precisionLost | O | 1 | Optional | Precision Lost in Result | |
| flagRaised | O | 1 | Optional | One of the Implemented Flags are raised | |
| select | I | 1 | Optional | Select Operation | Only in wrapper |
I: Input O: Output
Parameters
Following parameters can be used to modify the size of operation and the output flags.
|Parameter|Possible Values|Description|
| :----: | :-----: | ---- |
| BIT_SIZE | 32, 64 | Operation Size |
| ROUNDING_TYPE | bool | Rounding to the closer value, when disabled floor |
| ENABLE_FLAGS_MASTER | bool | Master enable for flags |
| ENABLE_FLAGS_COMMON | bool | Enable flagRaised |
| ENABLE_FLAGS_OF | bool | Enable overflow |
| ENABLE_FLAGS_ZERO | bool | Enable zero |
| ENABLE_FLAGS_NaN | bool | Enable NaN |
| ENABLE_FLAGS_PLost | bool | Enable precisionLost |
For custom exponent formats, one can enable "value override" mode with FORMAT_OVERRIDE and enter corresponding widths to EXPONENT_SIZE_OR and FRACTION_SIZE_OR. Sign bit is always 1 bit. Custom formats are not tested.
Performance and Resource Utilization
All values in this section are for Xilinx Artix-7 (XC7A100TCSG324-1) FPGA. (Without Rounding/With Rounding)
Single-Precision Adder
- Utilization after synthesis: 473/502 LUT as Logic
- Maximum clock frequency (for input output registers): 65/55 MHz
Double-Precision Adder
- Utilization after synthesis: 985/1007 LUT as Logic
- Maximum clock frequency (for input output registers): 50/40 MHz
Simulation
Test benches will both generate a waveform and display overview of the test cases. Overview messages show operands, result, manually calculated expected result, and flag information.
convertFloat.py can be used to help with verification. It should convert values between formats. However this script is not thoroughly tested.
Test
Hardware tests of all modules is done by a VIO and placing a register between VIO and module ports.
Status Information
Last Simulation:
- Single-Precision Adder: 1 December 2022, with Icarus Verilog.
Issues
Nothing so far.
For newly found bugs; contact me, open an issue at gitlab (preferred) or github.
