soDLA

Thanks for HuiX, rgb000000, [CristinaZN], Leway for contribution, and also, chisel creators for help.

In addition to the original chisel-version of NVDLA, we have several additions, testing a neural network in chipyard, formal verifications, more docs to facilitate the specification process, and example customized accelerators under construction.

Lastest: We provide the prebuilt nvdla_vp

Smoke Test Setup

The whole environment is accomplished by chipyard. soDLA integration of latest chipyard(1.10.0) is now successful.

Paste soDLA and sodla-wrapper to chipyard/generators. The file structure should be like

 chipyard--->generators--->soDLA
                        |->sodla-wrapper

In chipyard/build.sbt, add sodla-wrapper

lazy val sodla = (project in file("generators/sodla-wrapper"))
  .dependsOn(rocketchip)
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

In chipyard/build.sbt, within the definition of chipyard, add sodla

lazy val chipyard = (project in file("generators/chipyard"))
  .sourceDependency(testchipip, testchipipLib)
  .dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
    sha3, // On separate line to allow for cleaner tutorial-setup patches
    dsptools, `rocket-dsptools`,
    gemmini, icenet, tracegen, cva6, sodla,nvdla, sodor)
  .settings(libraryDependencies ++= rocketLibDeps.value)
  .settings(commonSettings)

In DigitalTop.scala under chipyard/generators/chipyard/scala, insert

with np.blocks.dla.CanHavePeripherySODLA

within the option of DigitalTop.

In MMIOAcceleratorConfigs.scala under chipyard/generators/chipyard/scala/config, add a configuration of soDLA integrated soc

class SmallSODLARocketConfig extends Config(
  new np.devices.sodla.WithSODLA("small") ++               // add a small NVDLA
  new freechips.rocketchip.subsystem.WithNBigCores(1) ++
  new chipyard.config.AbstractConfig)

Compile software program

In chipyard/generators/soDLA/test, we prepare two testing programs, one is a direct convolution, another is an image convolution. To compile it under riscv

$ make

In chipyard/sims/vcs or chipyard/sims/verilator

$ rm -rf ../../generators/sodla-wrapper/target
$ make debug -j16 CONFIG=SmallSODLARocketConfig

You should see the simulation program generated by vcs/verilator, to run the program:

$ ./simv-chipyard-SmallSODLARocketConfig-debug ../../generators/soDLA/test/dc_1x1x8_1x1x8x1_int8_0/dc_1x1x8_1x1x8x1_int8_0.riscv 

Verification Plan

Since soDLA's main purpose is to design and reuse an industry-level accelerator. We provide the following modules in formal seq verifications between nvdla golden verilog models for the moment, and those modules are commonly used: apb2csb, csb_master, csc(dl only), glb, nocif

Golden cmodels for DPV verifications are under construction.