Logik

Logik

Logik is an open source FPGA tool chain with support for high level language parsing, synthesis, placement, routing, bitstream generation, and analysis. Users enter design sources, constraints, and compile options through a simple SiliconCompiler Python API. Once setup is complete, automated compilation can be initiated with a single line run command. Logik relies on the Logiklib project for all architecture and device descriptions.

Logik supports most of the features you would expect in a commercial proprietary FPGA tool chain.

| Feature | Status | |--------------------------|--------| | Design languages | SystemVerilog, Verilog, VHDL | DSP synthesis | Supported | RAM synthesis | Supported | Timing constraints (SDC) | Supported | Pin Constraints (PCF) | Supported | Bitstream generation | Supported | IP management | Supported | Remote compilation | Supported | Multi-clock designs | Supported | Supported devices | Logiklib devices

Getting Started

The Logik tool chain is available through PyPi and can be installed using pip.

python -m pip install --upgrade logik

All open source FPGA pre-requisites can be installed via the SiliconCompiler sc-install utility.

sc-install -group fpga

The following example illustrates some essential Logik features. For complete documentation of all options available, see the SiliconCompiler project.

import siliconcompiler
from logik.flows.logik_flow import LogikFlow
from logiklib.zeroasic.z1000 import z1000

# 1. Create a Design object to hold source files and constraints.
design = siliconcompiler.Design('adder')
design.add_file('adder.v', fileset="rtl")
design.set_topmodule('adder', fileset="rtl")

# Create an FPGA project
project = siliconcompiler.FPGA(design)

# Assign file sets to use for elaboration
project.add_fileset('rtl')

# Select the rtl2bits flow to use
project.set_flow(LogikFlow())

# Load FPGA part settings and associated flow and libraries.
project.set_fpga(z1000.z1000())

# User defined options
project.option.set_quiet(True)

# Run compilation
project.run()

# Display summary of results
project.summary()

[!NOTE] The required files can be found here

Examples

• Ethernet: Ethernet MAC compiled for the z1000 architecture.
• Adder: Small adder example compiled for the z1000 architecture.
• Picorv32: picorv32 RISC-V CPU example compiled for the z1062 architecture.

Documentation

• Logik Documentation
• SiliconCompiler Documentation

Installation

Logik is available as wheel packages on PyPI for macOS, Windows and Linux platforms. For a Python 3.8-3.12 environment, just use pip to install.

python -m pip install --upgrade logik

Running natively on your local machine will require installing a number of prerequisites:

• Silicon Compiler: Hardware compiler framework
• Slang: SystemVerilog Parser
• Yosys: Logic synthesis platform
• Wildebeest: High-performance synthesis yosys plugin
• VPR: FPGA place and route
• FASM: FPGA assembly parser and generator
• OpenSTA: Production-grade static timing analysis engine

We recommend using the SiliconCompiler sc-install utility to automatically install the correct versions of all open source FPGA tool dependencies.

sc-install -group fpga

Detailed installation instructions can be found in the SiliconCompiler Installation Guide.

License

The Logik project is licensed under the open source Apache License 2.0. For licensing terms of all dependencies, visit dependency repository.

Issues / Bugs

We use GitHub Issues for tracking requests and bugs.