Learn RISC-V

A community-driven, continuously updated compilation of RISC-V learning resources. Content is organized by topic and experience level to help you discover courses, software, documentation, and articles efficiently.

RISC-V is an open standard Instruction Set Architecture (ISA) based on established Reduced Instruction Set Computer (RISC) principles.

👋 Want to learn about RISC-V? Check out the Beginner-Level or Intermediate-Level learning resources.

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Learn RISC-V

➕ Making Contributions

We love contributions! Check out contributing.md for more info. Thank you for your interest in contributing to our RISC-V tutorial compilation.

📙 Resources

Learning Resources for RISC-V

🟢 Beginner-Level Resources

For those with little or no knowledge of digital logic design. Consider starting with Digital Design & Computer Architecture (RISC-V Edition) and then progressing to intermediate-level courses like RVfpga.

| Resource | Author(s) | Description | Access | Date Added | |---|---|---|---|---| | An Introduction to Assembly Programming with RISC-V | Prof. Edson Borin | Teaches RISC-V assembly programming concepts. | Webpage | 2024-05-03 | | Architecture 1005: RISC-V Assembly | OpenSecurityTraining | Security-focused exploration of RISC-V ISAs and extensions. | Course videos | 2024-04-15 | | Basic Computer Architecture | Smruti R. Sarangi | Computer architecture fundamentals. | Website | 2024-12-27 | | Computer Architecture Basics | CTU Prague – FEE (Pavel Piša) | Course covering computer architecture basics, including CPU design and speculative execution. | Course videos | 2024-04-16 | | Creating a RISC-V from scratch! | Lucas Teske (Teske's Lab) | Learning livestream series focused on creating an RV32E that runs on FPGAs. | YouTube (Portuguese) | 2024-10-18 | | Digital Design & Computer Architecture RISC-V Edition | Sarah L. Harris, David M. Harris | Foundational digital logic design and RISC-V processor implementation. | Amazon | 2024-10-01 | | Easy RISC-V | Vivian “dramforever” Wang | RISC-V assembly tutorial with interactive emulator (RV32I and some privileged arch). | Webpage | 2025-10-30 | | Hands-on RISC-V Processor Design | Rahul Behl | Dive into RISC-V processor design using SystemVerilog. | QuickSilicon | 2024-10-01 | | learn-FPGA episode I: from blinky to RISC-V | Bruno Levy | Design an FPGA-based RISC-V softcore starting from a basic Verilog blinker. | GitHub | 2024-10-01 | | LinuxFoundationX: Building a RISC-V CPU Core | Steve Hoover | Free course on RISC-V microarchitecture design using open-source tools. | edX course | 2024-10-01 | | Nand2Tetris | Noam Nisan, Shimon Schocken | Build a computer from logic gates using a hardware simulator. | Website | 2024-10-01 | | RISC-V Assembly Introduction (Portuguese) | Gabriel G. de Brito | Basics of RISC-V IM architecture with the EGG emulator. | Course videos | 2024-06-04 | | Step-by-step RISC-V Compiler Development | Shao-Ce Sun | Practical guide to RISC-V C compiler development. | Teaching resources · Course videos (Chinese) | 2024-03-20 | | Step-by-step RISC-V OS Development | Chen Wang | Practical guide for developing RISC-V operating systems. | Teaching resources · Course videos (Chinese) | 2024-05-03 | | The RISC-V Reader: An Open Architecture Atlas | David Patterson, Andrew Waterman | Introduction to the RISC-V instruction set. | RISC-V Reader | 2024-05-03 | | Writing a RISC-V OS From Scratch | Seiya Nuta | Write an OS for RISC-V in about 1,000 lines of code. | Webpage | 2025-07-27 | | Why Your Phone Is So Fast: The Sports Car vs. The Truck | David Patterson | How do we keep making computers faster? | Webpage | 2025-02-09 |

🔵 Intermediate-Level Resources

Advanced materials for learners familiar with digital logic and basic architecture.

| Resource | Author(s) | Description | Access | Date Added | |---|---|---|---|---| | Computer Architecture: A Quantitative Approach (6th Edition) | David Patterson, John Hennessy | Advanced topics including ILP and GPU architectures, using RISC-V. | Amazon | 2024-10-01 | | Computer Organization & Design (RISC-V Edition) | David Patterson, John Hennessy | In-depth study of RISC-V ISA and processor implementation. | Amazon | 2024-10-01 | | HaDes-V | Tobias Scheipel | The Instruction Guide and code template (OER) for microcontroller design using the HaDes-V RISC-V-based processor. | GitHub · Instruction Guide | 2024-12-18 | | Learn with SHAKTI | Shakti – RISE Lab, IITM | Tutorials on RISC-V assembly programming using the RISC-V toolchain. | Learn with Shakti | 2023-12-21 | | learn-FPGA episode II: pipelining | Bruno Levy | Extends the basic RISC-V softcore from episode I with pipelining and performance optimizations. | GitHub | 2024-10-01 | | LinuxFoundationX: RISC-V Toolchain and Compiler Optimization Techniques | Aditya Kumar | RISC-V toolchain internals and compiler optimizations. | edX course | 2024-10-01 | | RISC-V Optimization Guide | RISE Project | Actionable optimization recommendations for RISC-V software developers. | GitLab | 2024-02-19 | | RV64GC Linker from Scratch in Go | Yang Liu, PLCT Lab | Build an RV64GC linker from scratch in Go. | GitHub · Course videos (Chinese) | 2024-04-24 | | RVfpga (Extended): Understanding Computer Architecture | Sarah Harris, Daniel Chaver-Martinez | Updated RVfpga course with FPGA and simulation tools. | RVfpga v3.0 downloads | 2024-06-02 | | RVfpga: Computer Architecture with an Industrial RISC-V Core | Sarah Harris, Daniel Chaver-Martinez | Hands-on learning with a commercial RISC-V SoC on FPGAs. | edX course | 2024-10-01 | | Teaching experiences with RVfpga | ARTECS Group, Complutense University of Madrid | How RVfpga and the Ripes simulator were used in two UCM courses. | GitHub | 2024-10-18

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Install / Use

README

Learn RISC-V

Star History

👉 Table of Contents

➕ Making Contributions

📙 Resources

Learning Resources for RISC-V

🟢 Beginner-Level Resources

🔵 Intermediate-Level Resources