Overview

This repository centers around documenting modern ways of developing logic for and programming Atmel (Now Microchip) 5V GAL PLD and CPLD parts under recent Linux (Ubuntu 22.04) and Windows 10 22H2 versions.

• (Modern/active equivalent of the PAL16V8 and GAL16V8 parts)
• (Modern/active equivalent of the PAL22V10 and GAL22V10 parts)
• (Active replacement for the EPM7032)
• (Active replacement for the EPM7064)
• (Active replacement for the EPM7128)

These parts are still active and highly worth considering wherever:

• 5V logic is a requirement, avoiding level shifting, low latency (7ns), instant-on & non-volatile, and situations needing Hi-Z / Open-collector states.
• Prototyping / Iteration (reprogrammable)
• Learning about logic: Through-hole / soldering-friendly is desired: All 16V8 or 22V10 parts are available in DIP packages; ATF150x parts are available in PLCC packages that can be placed in through-hole PLCC sockets. SMD packages are available for any of the parts.
• Replacing large quantities of various TTL/CMOS Logic Gates (74-series logic)

In short, these chips work very well wherever the above requirements are necessary, however, the software (and device programming) experience can be incredibly challenging owing to outdated and buggy software.

This repository aims to make it easier to work with these parts and hopefully keep them active for years to come.

This is a "Choose your own adventure novel". Covered here are many approaches and tradeoffs:

• <a href="#old-approach-wincupl-16v8-22v10-and-atf150x">Using the WinCUPL IDE (Erratic, unreliable)</a>
• <a href="#5vcomp-the-cupl-compiler--your-favorite-text-editor-or-ide-16v8-22v10-and-atf150x">Using just the CUPL.EXE compiler from WinCUPL directly with some wrapper scripts here (5vcomp). Works in Windows/Linux. (recommended)</a>
• <a href="#quartus-free-verilog-vhdl-schematic-capture-indirect-support-for-atf150x-linux-or-windows">Using Quartus (only for the CPLD. Works by first targeting a similar Altera CPLD and then using the POF2JED utility to convert.) Windows/Linux</a>
• <a href="#absurd-approach-fusemaps-by-hand-16v8--22v10">Making your own fusemap / .JED file with nothing more than a datasheet and text editor. Maybe need some graph paper...</a>
• Experimental approaches with Yosys (Only for the CPLD parts. EDIF is fed into the Atmel fitter)
• Several Approaches to reverse-engineering a .JED file back into logic equations.

<details> <summary>Scope: Expand here for why similar parts not covered</summary>

• The intention is primarily to make it easier to work with parts that are still active so they do not go NRND and eventually disappear from the market. While there are gems here for other related historical parts, this is not the focus of this repository.
• The ATF1500 is not covered because it is a more expensive part and does not support JTAG programming. It is fundamentally different from the ATF1502, ATF1504, and ATF1508
• The ATF750 and ATF2500 are also not covered for similar reasons. Other chips are almost certainly a better choice.
  • The ATF2500C might be worth examining in spite of the somewhat high cost due to being available in a DIP-40 package and thus breadboard friendly. Without understanding the programming algorithm however, it would be of use to very few people as no recent/affordable device programmers support this chip.
• We only consider true 5V parts (not merely parts with 5V tolerant inputs, of which there are many more).
  • 3.3V parts cannot supply the minimum of 3.6V to drive the input of a 5V CMOS part high, so 5V tolerant parts are not enough in many cases. Even the parts covered here may not necessarily be capable of the required VoH as their output voltage drops off quickly under load. In these cases, pullup resistors can be considered.[^2]
  • Notably, however, driving 5V TTL inputs from a 3.3V part, on the other hand, is not a problem. A 5V TTL input has a threshold of 2V.
• 3.3V parts are not considered: There are simply better choices that are well documented. Also, the CPLD parts have VccIO inputs, so you can technically use them in 3.3V designs just as well.
• The following 5V IO capable parts probably should be covered, but they're already well supported, documented, modern tools, etc.
  • The Greekpak devices
  • The Cypress PSoC5LP (An ARM Cortex M3 with CPLD-like logic blocks), available in 68-pin QFN, 100-pin TQFP
• Any parts that are NRND or inactive are not covered, as we consider what can be reliably and sensibly purchased.
• Since all of the parts considered here are still in full production (as of 2023), they can be used in production designs.
• For the ATF150x CPLD parts specifically:
  • The parts ending in 'BE' are not covered here as they seem to be very expensive. In principle these are interesting because they have multiple IO bank voltages.
  • The parts ending in 'ASV' are 3.3V only, however, these are supported just fine in the workflows discussed here. Incidentally, the 'AS' devices can be operated at 3.3V IO through the VccIO pins. The lower pincount (44-pin) devices to not show VccIO pins in their datasheet, but it does seem to be the case that two pins are Vcc and two are VccIO, so this is possible as well.
• The PIC16F131xx devices have Configurable Logic Blocks that are capable of some interesting functionality. Additionally, their functionality under the hood has been documented by Mark Omo here https://mcp-clb.markomo.me/
• For applications where 5-Volt tolerant operation is acceptable, it might be worth considering the ispMACH4000 series. Parts such as the LC4032ZE are available in a somewhat soldering friendly TQFP, however there are likely similar challenges with software.
  • Vendor Tools:
    • ispLEVER v3.1 (2003)
    • ispLEVER v4.0 (2004)
    • ispLEVER Classic v1.8 (2014)
    • ispLEVER Classic v2.0 (2015)
  • Open source paths for these parts:
    • https://github.com/bcrist/re4k
    • https://github.com/bcrist/Zig-LC4k
    • Vendor Fitter: C:\ispLEVER_Classic2_1\ispcpld\bin\lpf4k.exe

</details>

News and Status

• Microchip has released the PIC16F13145 (Jan 2024?)
  • This chip combines a microcontroller with configurable logic blocks (CLB) which may well suit the needs of what you are otherwise seeking on this page.
• Microchip has annouced EOL for a number of ATF150x devices specifically in PLCC packages on June 2024. There are a few variants where PLCC packages are still available for these (at the very least, the ATF1502 is still available in PLCC), and all other package types are unaffected.
• Microchip has released WinCUPL II (v1.0.0 beta) on August 6th, 2025
  • The revision history only mentions adding compatability with Windows 10/11
  • Not mentioned in the release notes is that the included fitters for the ATF150x devices are now the latest version: 1918 (3-21-07) within WinCUPL II.
  • This repository and the utilities within were adamant about requiring the new fitters and the directions here recommended extracting these from Atmel Prochip. With WinCUPL II, this is no longer necessary -- the latest fitters come with WinCUPL II. Much of this repository is therefore out of date.

Background on digital logic.

This repository isn't intended to be an introduction to digital logic, but a brief review and compare/contrast to similar things is provided here.

<details> <summary>Expand here for tutorials on Digital Logic</summary>

Ben Eater does a series of <a href="https://www.youtube.com/watch?v=KM0DdEaY5sY&list=PLowKtXNTBypGqImE405J2565dvjafglHU&index=6">Videos on Digital Logic</a> that are a really excellent introduction to some of the concepts here.

</details> <details> <summary>Expand here for a description of how these parts compare to ladder logic on a PLC</summary>

• Each rung's output in ladder-logic can be thought of as a single macrocell.
• The inputs on a rung can be "normally open" or "normally closed" (active high or low), and can consist of any number of inputs (or even the state of another macrocell). The inputs defined on a single rung are basically equivalent to a single product-term belonging to a macrocell. There can be multiple product terms defined that activate a given macrocell.

</details> <details> <summary>Expand here for details on how all of these compare to FPGAs</summary>

Such parts are the spiritual predecessors of more modern FPGAs. Key differences between FPGAs and PLDs:

• FPGAs are typically constructed from a large number of LUTs (Lookup tables). CPLDs use a sum-of-products structure.
• FPGAs typically expect to have their bitstream uploaded on powerup, requiring an external EEPROM. PLDs are typically non-volatile and instantly ready upon powerup.
• FPGAs usually support more standard means of programming, whereas many PLDs required specialized device programmers.
• From input to output, CPLDs can be thought of as shallow but wide, theoretically having lower propagation delays (in practice, if we're talking about 5V logic, don't expect better than 7ns). FPGA have much deeper internal logic but are composed of LUTs with relatively tiny input widths (LUT4, LUT5, etc.).
• There are likely exceptions to all of the above in some parts. These are not hard rules.

</details>

Requirements

A high-level overview of what is required:

• Basic understanding of digital logic.