Serial VGA Controller

A VGA controller built around an 8‑bit PIC18F47K42, capable of generating 16 colors at an impressive 360×480 resolution, while using minimal external components. It is controlled through a UART interface, accepts ANSI‑style escape sequences and supports multiple screen modes.

You can watch a short Demo Video showcasing the controller in action.

The VGA History

The VGA standard and its corresponding controller were developed by IBM in 1987 and within the following three years it dominated the market of IBM-compatible computers. It supported a resolution of 640x480 with 16 colors and used a 15-pin input interface.

The standard was largely based on the older and well-established NTSC analog television standard, retaining many technical characteristics in order to facilitate the creation of VGA-to-TV converters. It maintained the same vertical resolution of 525 horizontal lines, of which only 480 are visible, while it chose a horizontal scanning frequency of 31.469 kHz, exactly double that of the NTSC standard.

Its operating principle is based on the serial scanning of the screen, line by line (from left to right, from top to bottom). For proper synchronization with the display, two synchronization signals are generated, whose active portion is at a logical low level:

The horizontal synchronization pulse (HSYNC), which is activated at the beginning of each line, and The vertical synchronization pulse (VSYNC), which is activated at the end of each frame to restart scanning from the top of the screen. In addition, it produces three analog signals with levels ranging from 0 V up to 0.7 V, corresponding to the RGB (Red, Green, Blue) color channels.

The digital signals anatomy

The VGA standard imposes strict specifications regarding the frequency and structure of the generated signal, which consists of two main components: the horizontal and vertical synchronization pulses.

Proper timing ensures the stable and reliable display of the image on the screen, synchronizing the rendering of each line (scanline) and each frame. All the individual time intervals are based on a unified clock frequency, known as the Pixel Clock. The Pixel Clock frequency is 25.175 MHz. Based on this frequency, both the horizontal and vertical refresh rates are calculated, which are critical for the correct refresh of the image on the screen.

<div align="center">

| Scanline Part | Cycles | Duration (μs) | | :------------ | :----: | ------------: | | Active Area | 640 | 25.42 | | Front Porch | 16 | 0.64 | | Sync Part | 96 | 3.81 | | Back Porch | 48 | 1.91 | | Scanline | 800 | 31.78 |

<p><em>HSYNC timings</em></p> <img src="./docs/pics/hsync.svg" width = "100%" alt="HSYNC signal" />

| Frame Part | Lines Count | Duration (ms) | | :------------ | :----------: | ------------: | | Active Area | 480 | 15.25 | | Front Porch | 10 | 0.32 | | Sync Part | 2 | 0.06 | | Back Porch | 33 | 1.05 | | Full Frame | 525 | 16.68 |

<p><em>VSYNC timings</em></p> <img src="./docs/pics/vsync.svg" width = "100%" alt="VSYNC signal" /> <p><em>VSYNC signal</em></p>

 

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Analog RGB signals

The transmission of color information is carried out through an analog RGB signal (Red, Green, Blue).
The overall signal is separated into three independent channels, each carrying the information for one primary color:

• Red channel
• Green channel
• Blue channel

The signal level of each channel ranges from 0.00 V to 0.70 V, where:

<div align="center">

| Level (Volt) | Brightness | | :----------: | -------------------------- | | 0.00 | Absence of Color (Black) | | 0.35 | Medium Brightness Color | | 0.70 | Maximum Brightness Color |

<p><em>RGB Signal Levels</em></p> </div>

This range is generated by a digital-to-analog converter (DAC), which converts the digital value of each color into the corresponding analog voltage level.
It is evident that three DACs are required, one for each color channel.

The combined activation of the RGB channels leads to additive color synthesis, which enables the creation of a wide overall color spectrum.

<div align="center"> <img src="./docs/pics/rgb.png" alt="rgb" style="max-width: 100%;" /> <p><em>Additive Color Mix</em></p> </div>

Hardware Architecture

The VGA controller is implemented using a PIC 18F47K42 microcontroller, squeezing out every bit of its available horsepower through efficient utilization of its peripherals.

The choice of an 8-bit microcontroller was not accidental. While employing a 32-bit ARM Cortex‑M device or an FPGA would have made the implementation considerably easier, it would undermine the very objective of the project. The aim was not to build a high‑performance VGA controller, but to prove that even a resource‑limited microcontroller, when paired with smart peripheral management and disciplined programming, can satisfy the strict requirements of the VGA standard and produce a continuous, flicker‑free video signal.

To better illustrate the overall system design, the hardware architectural overview is presented in the diagram below:

<div align="center"> <img src="./docs/pics/architecture_overview.svg" alt="hw overview" style="max-width: 100%;" /> <p><em>Hardware Architectural Overview</em></p> </div>

As shown above, the system consists of three major independent functional units, which cooperate to generate all the signals required for driving the display.
Specifically, the hardware includes two internal and one external entity. Those are:

• Synchronization Signal Generation Unit (internal)
  Responsible for producing the horizontal and vertical synchronization signals.

• Visible Area Signal Generation Unit (internal)
  Generates the intersection of the horizontal and vertical active areas and enables the multiplexers.

• RGB Analog Signal Generation Unit (external)
  Implemented outside the microcontroller and includes the multiplexers and digital‑to‑analog converters that produce the analog RGB signal.

SYNC Signals Generation Unit

The SYNC signals are generated exclusively in hardware using the MCU peripherals.
As a result, the microcontroller, operating at 14.3182 MIPS, is able to maintain precise timing for horizontal and vertical synchronization without imposing additional software overhead.
This hardware‑based generation ensures deterministic signal edges, minimizes jitter, and allows the CPU core to remain available for higher‑level tasks.

<div align="center"> <img src="./docs/pics/sync_signals.svg" alt="sync" style="max-width: 100%;" /> <p><em>SYNC signals generator</em></p> </div>

Note that the clock used is not the standard 25.175 MHz.
This frequency would be out of specification for the PIC18F47K42, whose maximum supported external clock input is 16 MHz.
Instead, given the partial backward compatibility with the NTSC standard, a passive crystal of 14.3182 MHz has been selected.
This frequency is commonly used in televisions that support NTSC analog signals and is both widely available and extremely low cost.

The MCU is set to use 4× PLL internally.
However, due to the PIC18 architecture, the system clock is always divided by 4 to obtain the instruction clock: $OSC / 4$

With a 14.3182 MHz external crystal and the PLL set to 4×, the internal oscillator becomes: $14.3182,\text{MHz} \times 4 = 57.2728\ \text{MHz}$

and the instruction clock becomes: $57.2728,\mathrm{MHz} / 4 = 14.3182\ \mathrm{MHz}$

Therefore, the instruction clock ends up exactly equal to the crystal frequency, and the pixel clock becomes effectively 14.3182 MHz, matching the instruction rate.

By making this choice, the maximum pixel clock frequency corresponds to:

$14.3182,\mathrm{MHz} / 25.175\ \mathrm{MHz} = 0.5687$ → 56.87% of the standard

Thus, the cycles corresponding to each scanline become: $800 \times 0.5687 = 455$

This ensures perfect alignment with the timing requirements of the standard, since: $455 / 14.3182,\mathrm{MHz} = 31.78\ \mu s$

At the same time, this choice limits the maximum horizontal resolution: $640 \times 0.5687 = 364$ pixels

Although this value appears significantly lower than the original 640 pixels, it is entirely acceptable for data visualization and far exceeds the typical resolutions achieved by 8‑bit era computers.

The following table shows the recalculated VGA horizontal timing parameters when the pixel clock is derived from a 14.3182 MHz crystal.
Each section has been proportionally adjusted to match the lower clock frequency, while the overall length remains 31.78 µs, perfectly matching the VGA standard:

<div align="center">

| Section | Cycles | Time (µs) | | :------------ | :----: | --------: | | Active Area | 364 | 25.42 | | Front Porch | 9 | 0.63 | | Sync Part | 55 | 3.84 | | Back Porch | 27 | 1.89 | | Whole line| 455| 31.78 |

<p><em>Adjusted HSYNC signal</em></p> </div>

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Visible Area Signal Generation Unit

The Visible Area Video signal is also hardware‑assisted, further reducing the processing load on the MCU.
It utilizes two PWM modules to generate the required timing intervals:

• PWM6 produces a signal with an active duration of 1.89 µs, corresponding to the Horizontal Back Porch.
• PWM7 produces a signal with an active duration of 27.31 µs, equal to the sum of the Horizontal Active Video and Horizontal Back Porch.

The intersection of the inverted PWM6 signal and the PWM7 signal defines the Horizontal Active Video interval.
The intersection of this interval with the corresponding interval of the vertical sy