ai4eda

A collection of design automation algorithms, methodologies, and tools for electronics/photonics, and emerging eda technologies

Contributed by Yuan Wang.

Content

<table> <tr><td colspan="2"><a href="#analog-circuit-optimization">1. analog circuit optimization</a></td></tr> <tr> <td>&ensp;<a href="#simulation-based">1.1 simulation-based</a></td> <td>&ensp;<a href="#learning-based">1.2 learning-based</a></td> </tr> <tr> <td>&ensp;<a href="#bayesian-optimization">1.3 bayesian optimization</a></td> <td>&ensp;<a href="#GNN">1.4 GNN</a></td> </tr> <tr><td colspan="2"><a href="#photonics">2. photonics</a></td></tr> <tr><td colspan="2"><a href="#survey">3. survey</a></td></tr> <tr><td colspan="2"><a href="#tools">4. tools</a></td></tr> </table>

analog circuit optimization

simulation-based

1. Two-Step RF IC Block Synthesis With Preoptimized Inductors and Full Layout Generation In-the-Loop. paper

   Ricardo Martins, Nuno Lourenço, Fábio Passos, Ricardo Póvoa.

2. Anaconda: simulation-based synthesis of analog circuits via stochastic pattern search. paper

   R. Phelps, M. Krasnicki, R.A. Rutenbar, L.R. Carley, J.R. Hellums.

3. A new metaheuristc combining gradient models with NSGA-II to enhance analog IC synthesis. paper

   F. Rocha, N. Lourenço, R. Póvoa, R. Martins, N. Horta.

4. Automated design of analog and high-frequency circuits. book

   B Liu, G Gielen, FV Fernández.

learning-based

1. AutoCkt: Deep Reinforcement Learning of Analog Circuit Designs. paper

   Keertana Settaluri, Ameer Haj-Ali, Qijing Huang, Kourosh Hakhamaneshi, Borivoje Nikolic.

2. GASPAD: A General and Efficient mm-Wave Integrated Circuit Synthesis Method Based on Surrogate Model Assisted Evolutionary Algorithm. paper

   Bo Liu, Dixian Zhao, Patrick Reynaert, Georges G. E. Gielen.

3. Electric Analog Circuit Design with Hypernetworks and a Differential Simulator. paper

   Michael Rotman, Lior Wolf.

4. GCN-RL Circuit Designer: Transferable Transistor Sizing with Graph Neural Networks and Reinforcement Learning. paper

   Hanrui Wang, Kuan Wang, Jiacheng Yang, Linxiao Shen, Nan Sun, Hae-Seung Lee, Song Han.

5. Learning to Design Circuits. paper

   Hanrui Wang, Jiacheng Yang, Hae-Seung Lee, Song Han.

6. An Efficient Analog Circuit Sizing Method Based on Machine Learning Assisted Global Optimization. paper

   Ahmet Faruk Budak, Miguel Gandara, Wei Shi, David Z. Pan, Nan Sun, Bo Liu.

7. Automated Design of Analog Circuits using Machine Learning Techniques. paper

   S Devi, Gourav Tilwankar, Rajesh Zele.

8. Trust-Region Method with Deep Reinforcement Learning in Analog Design Space Exploration. paper

   Kai-En Yang, Chia-Yu Tsai, Hung-Hao Shen, Chen-Feng Chiang, Feng-Ming Tsai, Chung-An Wang, Yiju Ting, Chia-Shun Yeh, Chin-Tang Lai.

9. DNN-Opt: An RL Inspired Optimization for Analog Circuit Sizing using Deep Neural Networks. paper

   Ahmet F. Budak, Prateek Bhansali, Bo Liu, Nan Sun, David Z. Pan, Chandramouli V. Kashyap.

10. Using ANNs to Size Analog Integrated Circuits. book

    João P. S. Rosa, Daniel J. D. Guerra, Nuno C. G. Horta, Ricardo M. F. Martins & Nuno C. C. Lourenço.

11. BagNet: Berkeley Analog Generator with Layout Optimizer Boosted with Deep Neural Networks. paper

    Kourosh Hakhamaneshi, Nick Werblun, Pieter Abbeel, Vladimir Stojanovic.

12. Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit Modeling. paper

    Juzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen.

13. A Gaussian Process Surrogate Model Assisted Evolutionary Algorithm for Medium Scale Expensive Optimization Problems. paper

    Bo Liu, Qingfu Zhang, Georges G. E. Gielen.

14. Automatic Selection of Process Corner Simulations for Faster Design Verification. paper

    Michael Shoniker, Oleg Oleynikov, Bruce F. Cockburn, Jie Han, Manish Rana, Witold Pedrycz.

15. Minimizing the Number of Process Corner Simulations during Design Verification. paper

    Michael Shoniker, Bruce F. Cockburn, Jie Han, Witold Pedrycz.

16. Analog circuit topological feature extraction with unsupervised learning of new sub-structures. paper

    Hao Li, Fanshu Jiao, Alex Doboli.

17. Late Breaking Results: An Efficient Learning-based Approach for Performance Exploration on Analog and RF Circuit Synthesis. paper

    Po-Cheng Pan, Chien-Chia Huang, Hung-Ming Chen.

18. A Circuit Attention Network-Based Actor-Critic Learning Approach to Robust Analog Transistor Sizing. paper

    Yaguang Li, Yishuang Lin, Meghna Madhusudan, Arvind Sharma, Sachin Sapatnekar, Ramesh Harjani, Jiang Hu.

19. Prioritized Reinforcement Learning for Analog Circuit Optimization With Design Knowledge. paper

    N.S. Karthik Somayaji, Hanbin Hu, Peng Li.

20. Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm. paper

    Ling-Yen Song, Tung-Chieh Kuo, Ming-Hung Wang, Chien-Nan Jimmy Liu, Juinn-Dar Huang.

21. CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit Simulation. paper

    Qiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen.

22. A Fast and Accurate Middle End of Line Parasitic Capacitance Extraction for MOSFET and FinFET Technologies Using Machine Learning. paper

    Mohamed Saleh Abouelyazid, Sherif Hammouda, Yehea Ismail.

23. Automatic analog schematic diagram generation based on building block classification and reinforcement learning paper

    Hsu, Hung-Yun and Lin, Mark Po-Hung

bayesian optimization

1. An Efficient Batch Constrained Bayesian Optimization Approach for Analog Circuit Synthesis via Multi-objective Acquisition Ensemble. paper

   Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng.

2. An Efficient Bayesian Optimization Approach for Automated Optimization of Analog Circuits. paper

   Wenlong Lyu, Pan Xue, Fan Yang, Changhao Yan, Zhiliang Hong, Xuan Zeng, Dian Zhou.

3. Batch Bayesian Optimization via Multi-objective Acquisition Ensemble for Automated Analog Circuit Design. paper

   Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng.

4. High-Dimensional Bayesian Optimization for Analog Integrated Circuit Sizing Based on Dropout and gm/ID Methodology. paper

   Chen Chen, Hongyi Wang, Xinyue Song, Feng Liang, Kaikai Wu, Tao Tao.

5. LinEasyBO: Scalable Bayesian Optimization Approach for Analog Circuit Synthesis via One-Dimensional Subspaces. paper

   Shuhan Zhang, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng.

6. Multi-objective Bayesian Optimization for Analog/RF Circuit Synthesis. paper

   Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng.

7. A Novel and Efficient Bayesian Optimization Approach for Analog Designs with Multi-Testbench. paper

   Jingyao Zhao, Changhao Yan, Zhaori Bi, Fan Yang, Xuan Zeng, Dian Zhou.

GNN

1. Pretraining Graph Neural Networks for few-shot Analog Circuit Modeling and Design. paper

   Kourosh Hakhamaneshi, Marcel Nassar, Mariano Phielipp, Pieter Abbeel, Vladimir Stojanović.

2. ParaGraph: Layout Parasitics and Device Parameter Prediction using Graph Neural Networks. paper

   Haoxing Ren, George F. Kokai, Walker J. Turner, Ting-Sheng Ku.

3. GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog Circuits. paper

   Kishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar.

4. **Layout