قال رسول الله صلى الله عليه وسلم ‏:‏ ‏ "‏إذا مات ابن آدم انقطع عمله إلا من ثلاث‏:‏ صدقة جارية ،أو علم ينتفع به، أو ولد صالح يدعو له‏"‏ ‏(‏‏(‏رواه مسلم‏)‏‏) </br>

The Prophet Muhammad (Peace be upon him) said, "When a person dies, his deeds come to an end except for three things: An ongoing charity whose benefit is continuous; or knowledge from which benefit continues to be reaped, or a righteous child who supplicates for him." </br> </br>

Salam, I'm Muhammad Aldacher 👋

📫 How to reach me: Linkedin</br>

-> [ Study Material ]</br> -> [ Projects ]</br> -> [ MSc Courses (SJSU) ]</br>

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Study Material

Here, I will try to organize a study roadmap for people interested in Analog & Mixed-Signal design, based on what I found useful during my studies:

1. Analog Design Basics
2. Digital Circuits Basics
3. PLLs (Phase-Locked Loops)
4. ADCs (Analog/Digital Converters)
5. LDOs (Low-Dropout Regulators)
6. RF receiver system
7. IO/SERDES system </br>..................................................................................

• Layout
• Cadence Tutorials
• Razavi References
• Razavi AnalogMind Articles - drive - linkedin </br>..................................................................................

• Interview Questions
• Resume-Building Docs

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Projects & Labs

|Topic| | Project | Year | |---:|---|---|---| | SERDES |||| | | 1 | RX DFE (1-tap) Design | 2021 | | | 2 | RX Active CTLE Design | 2021 | | | 3 | TX FIR Equalizer Design (CML) | 2021 | | | 4 | TX Driver Design: CM Vs VM | 2021 | | | 5 | Wireline Channel Characterization | 2021 | | | 6 | Transceiver for 10GbaseKR standard | 2013 | | ADCs & DACs |||| | | 6 | 8-bit Asynchronous SAR ADC design | 2020 | | | 7 | 1.5-bit Pipeline ADC with Boosted OpAmp| 2018 | | | 8 | Dynamic Comparator design | 2018 | | | 9 | Bootstrapped Switch design | 2018 | | | 10| Current-steering DAC design | 2018 | | | 11| Modeling of 4-bit Flash ADC & DAC | 2018 | | | 12| Modeling of 10-bit Pipeline ADC & DAC | 2018 | | Clocking |||| | | 13| 10-GHz Standing-Wave based Clock-Distribution Network design| 2021 | | | 14| 1.9-GHz PLL design | 2018 | | LDOs |||| | | 15| LDO Regulator design | 2018 | | RF |||| | | 16| 1.9-GHz-Rx-frontend blocks | 2018 | | | 17| 2.4-GHz LNA design | 2016 | | Layout |||| | | 18| 8x8 SRAM array design | 2017 | | | 19| 8-bit Microprocessor | 2013 | | FPGA |||| | | 20| FPGA Design of a Digital/Analog Clock Display | 2017 | | Signal Processing|||| | | 21| DTFT & Convolution | 2020 | | | 22| Z Transform & Tone Reduction | 2020 |

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MSc Courses (SJSU)

| | Course | Year | Semester | |---:|---|---|---| | 1 | EE223 - Analog ICs Design| 2016 | Fall | | 2 | EE220 - Radio Frequency Integrated Circuits Design I| 2016 | Fall | | 3 | EE178 - Digital Design with FPGA| 2017 | Fall | | 4 | EE224 - High Speed CMOS| 2017 | Fall | | 5 | EE288 - Data Conversion for AMS ICs| 2018 | Spring | | 6 | EE295 - Technical Writing| 2018 | Spring | | 7 | EE230 - Radio Frequency Integrated Circuits Design II| 2018 | Fall | | 8 | EE250 - Probability| 2019 | Fall | | 9 | EE210 - LinearSystems| 2020 | Fall |

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