The ZAP Processor : An ARM V5TE Compliant Soft Core for FPGA with Cache and MMU (https://github.com/krevanth/ZAP)

Copyright (C) 2016-2024 Revanth Kamaraj (krevanth) <revanth91kamaraj@gmail.com>.

IMPORTANT:

• Note that https://github.com/krevanth/ZAP was unintentionally deleted but has now been restored to the same URL from backups on 23/11/2023. Sadly, the fork list, issues, stars and watchers couldn't be restored.
• DUE TO THE ABOVE, ALL PREVIOUS FORKS OF https://github.com/krevanth/ZAP HAVE BEEN DETACHED FROM IT.
• DUE TO THE ABOVE, PLEASE VERIFY THAT YOU ARE VIEWING THE ORIGINAL REPO AT https://github.com/krevanth/ZAP TO AVOID ACCIDENTIALLY LOOKING AT FORKS/DETACHED FORKS/UNCONTROLLED COPIES.

REPO CREATION AND FIRST COMMIT DATE : AUG 29 2016. View First Commit ( Author=REVANTH KAMARAJ (KREVANTH) Hash=222f6751b88e98d88ec831fc87e2d919ba8b2419 Date=Aug 29 2016 )

License

Copyright (C) 2016-2024 Revanth Kamaraj (krevanth) <revanth91kamaraj@gmail.com>.

This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.

Authors

RTL Design

All of ZAP RTL is Copyright (C) 2016-2024 Revanth Kamaraj (krevanth) <revanth91kamaraj@gmail.com>.

Verification

Most of ZAP's test code is Copyright (C) 2016-2024 Revanth Kamaraj (krevanth) <revanth91kamaraj@gmail.com> except for the cases noted below:

Thanks to ElectronAsh for working on a 3DO video game project based around the ZAP core and helping me debug several issues.

Thanks to Erez Binyamin for adding Docker infrastructure support.

Notice

The repo https://github.com/krevanth/ZAP is the official, definitive and authoritative ZAP processor repository.

What happened to the repo's forks, issue history, stars and watcher list ?

The repo https://github.com/krevanth/ZAP was detached from its forks (as an unintended consequence) when the repo was made private and was then deleted from GitHub. The repo has now been restored at the same URL as before i.e., https://github.com/krevanth/ZAP from a combination of local backups. Those who have forked the repo before are encouraged to make a new fork based on https://github.com/krevanth/ZAP. Apologies for the inconvenience caused.

Unfortunately, the issue history, start, watchers list and the list of the repo's forks could not be restored.

Compatibility

The V5TE specification leaves certain features to be IMPLEMENTATION DEFINED or UNPREDICTABLE. These are discussed later in this document. Code relying on such features must be checked to ensure that the expectation from the hardware meets the ZAP implementation.

1. Introduction

The default processor specification is as follows (The table below is based on default parameters):

| Property | Value | | --------------------------------------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | | Max. Operating Frequency @ Artix-7 FPGA | ~120MHz @ xc7a75tcsg324-1<br/>~145MHz @ xc7a75tcsg324-2<br/>~170MHz @ xc7a75tcsg324-3<br/> | | Pipeline Depth | 17 | | Issue and Execution Width | Single issue, in order, scalar core, with very limited out-of-order completion for some loads/stores that miss in cache. | | Data Width | 32 | | Address Width | 32 | | Virtual Address Width | 32 | | Instruction Set Versions | V5TE (1999) without FPU | | L1 I-Cache | 8KB Direct Mapped VIVT Cache.<br/>64 Byte Cache Line<br/>Cache must be enabled, and utilized effectively, for peak performance. | | L1 D-Cache | 8KB Direct Mapped VIVT Cache<br>64 Byte Cache Line<br/>Cache must be enabled, and utilized effectively, for peak performance. | | I-TLB Structure | 4 x Direct mapped, one direct mapped TLB per page size. 4 entries for 1MB pages, 8 entries for 64KB pages, 16 entries for 4KB pages and 32 entries for 1KB pages. Each page size has a unique hardware buffer. | | D-TLB Structure | 4 x Direct mapped, one direct mapped TLB per page size. 4 entries for 1MB pages, 8 entries for 64KB pages, 16 entries for 4KB pages and 32 entries for 1KB pages. Each page size has a unique hardware buffer. | | Branch Prediction | Direct Mapped Bimodal Predictor. <br/>Direct Mapped BTB.<br>512 entries in T state (16-bit instructions).<br>256 entries in 32-bit instruction state. | | RAS Depth | 4 deep return address stack. | | Branch latency | 12 cycles (wrong prediction or unrecognized branch)<br>3 cycles (taken, correctly predicted)<br>1 cycle (not-taken, correctly predicted)<br>12 cycles (32-bit/16-bit switch)<br>18 cycles (Exception/Interrupt Entry/Exit) | | Fetch Buffer | FIFO, 16 x 32-bit. | | Bus Interface | Unified 32-Bit Wishbone B3 bus with CTI and BTE signals.<br/>BTE and CTI signals are used only when cache is enabled. |

A simplified block diagram of the ZAP pipeline is shown below. Note that ZAP is mostly a single issue scalar processor.

ZAP includes several microarchitectural enhancements to improve instruction throughput, hide external bus and memory latency and boost performance:

• The ability to continue instruction execution even when the data cache is being filled. The data cache features hit under miss capability. The processor stalls when an instruction that depends on the cache access is decoded.
• Direct mapped instruction and data caches. These caches are virtually indexed and virtually tagged. Individual caches allow code and data to be accessed at the same time. The sizes of these caches can be set during synthesis. Cache size is parameterizable. Cache line width may be set as well.
• The D-cache also stores the physical address of the cache line on write as this allows subsequent cache clean operations to avoid having to walk the page table again. This feature does increase resource usage but can significantly reduce cache clean latency.
• Direct mapped instruction and data memory TLBs. Having separate translation buffers allows data and code translation to happen in parallel. The sizes of these TLBs can be set during synthesis. Six different TLB memories are provides, each providing direct mapped buffering for sections, large page and small page, each for instruction and data (3 x 2 = 6). The sizes of these 6 memories is parameterizable.
• A 4-state bimodal b