Project Documentation

This documentation provides a concise overview of the modules in this repository and how to build / simulate them.

Modules:

• DF1 - Basic VHDL components (gates, latch, full adder, FSM)
• DF2 - Collections of small designs and simulations (BasicLogicGates, FSM_Protocols, IntermediateBlocks)
• DF3 - FPGA-focused projects (Counter, Decoder)
• DF4 - AXI4-Lite slave and GPIO (in progress)
• DV1 - Not found in repository (placeholder)
• DV2 - FilterDXI demonstration (VHDL filter with test vectors)
• DV3 - Verification/UVM project
• CPU0 - RISC-V SystemVerilog CPU core (instruction memory, datapath, control)

Refer to the individual module pages for details, file lists, and instructions.