KiCad to Verilog Generator

Introduction

This is a KiCad plugin for generating Verilog code from a KiCad 6.0 (or later) schematic.

This is useful if you are designing a retro circuit board, e.g. a CPU made out of discrete TTL chips, and want to simulate it. You would design your circuit in KiCad's schematic editor, convert it to Verilog, and use any one of the several free [Verilog simulators](List of HDL simulators - Wikipedia) available.

You would most certainly not use KiCadVerilog (KV) to write Verilog for an FPGA. In that case, you would just write the Verilog directly. As such, KV is, admittedly, a niche application.

It's important to understand exactly what KV will and will not do for you. It will help you immensely, but you will still need to write some Verilog code yourself.

KV takes the netlist generated by KiCad's schematic editor and converts it to Verilog. There are more details below, but essentially it generates Verilog wires for the KiCad nets, generates Verilog modules for the KiCad symbols (the components in your schematic) with appropriate port lists, and generates instantiations of the modules that pass the appropriate signals to the module. So all the wiring of your design is correctly converted to Verilog.

But KV doesn't know the functionality of the components in your design. So you still need to write the Verilog code that goes into the modules that KV generates (or find it on the web).

KV helps you integrate your Verilog code with the KV-generated Verilog code. In the KiCad schematic, each symbol has Properties, and those properties include a list of Fields. KV looks for custom fields, which you'll create, and uses them to insert the code you write into the generated Verilog. So you can simulate your design, modify the schematic, re-generate the Verilog, and have all your work automatically incorporated into the re-generated code.

(If your first thought is that you don't want to put a large chunk of Verilog code in the KiCad fields, don't worry: that's addressed later.)

KV does more, like detecting pull-up and pull-down resistors, and bypass capacitors. But this gives you the general idea and helps you decide whether KV will meet your needs. Let's get into the details.

Installing KiCadVerilog

If you are running under Windows: go to the Windows Start menu and select KiCad 6.0 Command Prompt (in the KiCad 6.0 folder). In the command prompt window that appears, give the command pip install pyparsing. If KiCad was running during this, exit and re-run it.

Next, install the plugin itself. Download the plugin's zip file. From the KiCad Project Manager, select Tools->Plugin and Content Manager. In the displayed window, click the Install from File... button at the bottom and select the zip file.

If Pcbnew was running while you did that, you'll need to select its Tools->External Plugins->Refresh Plugins menu. The KiCadVerilog icon should then appear on Pcbnew's toolbar.

Running KiCadVerilog

The following section, Understanding KiCadVerilog, explains exactly what KV does, and what you need to do to create a complete Verilog program. But let's do the easy stuff first: running KiCadVerilog.

First, generate a netlist for your schematic. To do this, run the Schematic Editor, select File->Export->Netlist..., click the Export Netlist button, and choose a file name.

Next, run the PCB Editor (even if you haven't created a PCB for this project yet). Click the KiCadVerilog button on the toolbar () or select Tools->External Plugins->KiCadVerilog. You'll see the following dialog box:

Enter the path of the netlist file you just exported. Give the path and name of the file where you would like the Verilog file generated, and click Generate Verilog.

Complex schematics might take a minute to process. Be patient. Errors, warnings, and messages will appear in the Results box when the Verilog generation is done.

Understanding KiCadVerilog

Overview

There are more details in the following sections. But the general approach to converting your schematic to Verilog is this:

1. Write (or find on the web) a Verilog module implementing the behavior of each component in your schematic. So, for example, if you have a 7402 quad NOR gate in your circuit, you need to write or find Verilog code that implements a quad NOR gate. Put these modules in one or more include files.

2. Export a netlist of your schematic from KiCad's Schematic Editor, run KiCadVerilog on it, and open the generated Verilog in a text editor.

3. For each module in the generated code, write an instantiation of the module from step 1 that implements that component's behavior. Usually, the instantiation will just be a single line of code that takes the arguments passed into the module, and re-arranges them to call the Verilog modules you wrote in step 1.

   These one line instantiations you're writing will not stay in the generated Verilog file. You're only writing them here because it's a convenient text editor, where you can see all the arguments to the module. But in step 4, you're going to copy the instantiations you write here, and paste them into fields in the KiCad schematic.

   Notice that if you use the same component multiple times, e.g. if you have multiple 7402 quad NOR gates in your design, the instantiations of them will all be the same. So you only have to write the instantiation once (but in the next step, you will copy that instantiation into a field for each 7402 in your schematic).

4. Go back to KiCad's Schematic Editor and bring up the symbol properties for each component. Create a VerilogInclude field and enter the name of the include file that has the implementation for that component. Create a VerilogCode field, and copy and paste the instantiation you wrote for that component.

   Since the Verilog you write is incorporated into the KiCad schematic, it will always be incorporated into the generated Verilog, without any additional effort on your part.

   Note that if you have multiple identical components, like multipe 7402s, you don't really need to create VerilogInclude fields for each of them. If just one of them includes the Verilog file you need, the generated Verilog code will have the necessary include statement.

5. Re-export the netlist and run KiCadVerilog on it. You should now have a file ready for Verilog simulation.

The Generated Verilog Code

A KiCad netlist contains nets and parts (i.e. the symbols or components in your schematic). The parts have pins (i.e. the pins on an integrated circuit, or the leads of components like resistors and capacitors). The netlist also contains information about which nets are connected to which pins.

Legal Names

Each net, part, and pin in the netlist has a name. The names are legal according to KiCad's rules, but Verilog has different rules. And so, in the Verilog code KV generates, the KiCad names are converted to legal Verilog names. Most illegal Verilog characters are converted to underscores. Characters that typically indicate inverse logic (*, ~, /) are converted to the letter n. Plus signs are converted to the word "plus" (so that a net named "+5V" becomes "plus5V"), and non-ASCII characters are converted to their hexadecimal codes.

Includes

The first code KV generates is a list of include directives. You specify which files to `include in the generated Verilog by adding VerilogInclude fields to symbols in your KiCad schematic (see below).

Top-Level Module

The generated top-level Verilog module is given a name based on the output file name specified in the dialog, above.

The top-level module's ports are determined by VerilogModulePort fields that you can specify in the symbol properties in the KiCad schematic (see below).

Wires

Within the top-level module, KV generates a Verilog wire for every net in the netlist. However, KV detects a small number of special-case wires.

KiCad has power port symbols, such as "+5V", "+3V3", etc. A net connected to one of these symbols gets its name from the symbol. KV looks for nets whose names start with a plus sign, or whose names are "Vdd" or "Vcc" (KV uses a case-insensitive comparison).

Those nets are assumed to be a logical 1 value. And so when KV generates a Verilog wire for them, it assigns that wire the value of 1. As a result, any pin tied to a positive voltage will be connected to a logical 1 in the Verilog code.

Similarly, if a net is named "GND" or "Vss" (case-insensitive), the generated Verilog wire is assigned a value of 0. Any pin tied to ground will be connected to a logical 0 in the Verilog code.

KV also recognizes nets that are being pulled up or pulled down. If a net is connected to a resistor, and the other end of that resistor is connected to net that was recognized as a positive voltage, then the first net is being pulled up, and a tri1 wire is generated in Verilog.

If a net is connected to a resistor that is connected to ground, the net is being pulled down and KV generates it as a tri0 wire.

KV recognizes a resistor as a part with two pins and whose KiCad description field contains the word "resistor" (case insensitive).

Module Invocations

After generating the wires, KV generates module invocations for each part (symbol) in your schematic, with the following exceptions:

• It does not generate module invocations (or modules) for pull-up and pull-down resistors.

• It does not generate module invocations or modules for bypass capacitors. Bypass capacitors are identified as parts