LED to believe

This project aims to provide LED blinking examples for all the FPGA dev boards in the world.

The goal is to provide a quick way to test your new FPGA board and get acquainted with using FuseSoC in your design flow.

Each FPGA board is implemented as a separate FuseSoC target and users are highly encouraged to add support for their any board at their disposal so that we can have a large collection.

How to use

This project is available in the FuseSoC base library, so if you have FuseSoC installed, you likely already have this project as well.

To check if it's available run fusesoc core list and check for a core called fusesoc:utils:blinky.

If it's not there, try to run fusesoc library update to refresh the core libraries and look again.

If it's still not there, or if you want to modify the project, e.g. to add support for an additional board, you can add LED to believe as a new core library with fusesoc library add blinky https://github.com/fusesoc/blinky. LED to believe will now be added as a new library and downloaded to fusesoc_libraries/blinky

To build for your particular board, run fusesoc run --target=<board> fusesoc:utils:blinky where <board> is one of the boards listed in the Board support section below.

Alternatively, run fusesoc core show fusesoc:utils:blinky to find all available targets.

There is also a simulation target available to test the core without any hardware. To use this, run fusesoc run --target=sim fusesoc:utils:blinky.

The simulation target has a number of target-specific configuration parameters that can be set. All target-specific parameters goes on the end of the command line (after the core name).

To list all simulation parameters, run fusesoc run --target=sim fusesoc:utils:blinky --help.

The simulation target depends on the vlog_tb_utils core which is found in another library. If you don't already have the fusesoc-cores library in your workspace, you can add it with fusesoc library add fusesoc-cores https://github.com/fusesoc/fusesoc-cores.

Example: To run four pulses with a simulated clock frequency of 4MHz and creating a VCD file, run fusesoc run --target=sim fusesoc:utils:blinky --pulses=4 --clk_freq_hz=4000000 --vcd.

The default simulator to use is Icarus Verilog, but other simulators can be used by setting the --tool parameter after the run command.

Currently supported simulators for this target are icarus, modelsim and xsim. To use e.g. modelsim run fusesoc run --target=sim --tool=modelsim fusesoc:utils:blinky.

What to do next

That was fun, wasn't it? And did you know that once you have gotten a LED to blink in this way, you are actually 90% of the way already to run a small SoC with a RISC-V CPU on the same board. Maybe your board is already supported? Or maybe you're up to the challenge of adding support for it. All it takes is to create a 16MHz clock and allocate an output pin to connect a UART. For more info, move on to learn about and run SERV, the world's smallest RISC-V CPU

Board support

The following boards are currently supported:

A-C4E6E1 Cyclone IV FPGA EP4CE6E22C8N Development Board

http://land-boards.com/blwiki/index.php?title=A-C4E6_Cyclone_IV_FPGA_EP4CE6E22C8N_Development_Board

AC701

https://www.xilinx.com/products/boards-and-kits/ek-a7-ac701-g.html

Altera Agilex 3 FPGA and SoC C-Series Development Kit

https://www.altera.com/products/devkit/a1jui000006ty5dmae/agilex-3-fpga-and-soc-c-series-development-kit

Altera Agilex 5 FPGA E-Series 065B Premium Development Kit

https://www.intel.com/content/www/us/en/products/details/fpga/development-kits/agilex/a5e065b-premium.html

AnalogMax

https://www.arrow.com/en/products/tei0001-03-16-c8/trenz-electronic-gmbh

afp27

http://www.armadeus.org/wiki/index.php?title=APF27

afp51

http://www.armadeus.org/wiki/index.php?title=APF51

Alchitry

Supports the Alchitry Cu, Au, and Au+ boards, plus the Io Element expansion board which can be used by any of the devices. Use the following targets:

• Cu: alchitry_cu
• Cu with Io Element: alchitry_cu_io
• Au: alchitry_au
• Au+: alchitry_au_plus
• Au+ with Io Element: alchitry_au_plus_io

All .bin files need to be loaded onto the devices using the Alchitry Loader (which is part of Alchitry Labs).

The cores for the Cu are built using IceStorm, and the cores for the Au and Au+ are built with Xilinx Vivado. Since Vivado does not recognize the devices natively, when building for the Au pass the --setup and --build flags. Otherwise, FuseSoC will fail when trying to load onto the device.

Alhambra II

https://alhambrabits.com/alhambra/

Alinx AX7A200B

https://www.en.alinx.com/Product/FPGA-Development-Boards/Artix-7/AX7A200B.html

arty_a7_35t/arty_a7_100t

https://digilent.com/shop/arty-a7-artix-7-fpga-development-board/

Atum A3 Nano (Terasic)

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1373

ax309

http://www.alinx.com/en/index.php/default/content/143.html

AXE5000 (Arrow)

https://github.com/ArrowElectronics/Agilex-5/wiki/Agilex-5-E-Series-AXE5000-Development-Platform

axku5

https://www.en.alinx.com/Product/FPGA-Development-Boards/Kintex-UltraScale-plus/AXKU5.html

This board contains a Xilinx Kintex UltraScale+ XCKU5P FPGA. A relatively large FPGA which is still supported by the (free) Vivado ML Standard Edition.

bemicro_max10

https://www.arrow.com/en/products/bemicromax10/arrow-development-tools

cmod_a7

This are two variants for this board:

• 15t has ~10K LUTs. Use --target=cmod_a7_15t
• 35t has ~20K LUTs. Use --target=cmod_a7_35t

https://digilent.com/reference/programmable-logic/cmod-a7/reference-manual

basys3

https://store.digilentinc.com/basys-3-artix-7-fpga-beginner-board-recommended-for-introductory-users/

c10lp_refkit

https://shop.trenz-electronic.de/en/TEI0009-02-055-8CA-Cyclone-10-LP-RefKit-10CL055-Development-Board-32-MByte-SDRAM-16-MByte-Flash

Chameleon96 (Arrow 96 CV SoC Board)

https://github.com/SoCFPGA-learning/Chameleon96

colorlight_5a75b

https://fr.aliexpress.com/item/32281130824.html

crosslink_nx_evn

https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/CrossLink-NXEvaluationBoard

cyc1000

https://shop.trenz-electronic.de/en/TEI0003-02-CYC1000-with-Cyclone-10-FPGA-8-MByte-SDRAM

Cisco HWIC-3G-CDMA

https://github.com/tomverbeure/cisco-hwic-3g-cdma

Waveshare CoreEP4CE10

https://www.waveshare.com/wiki/CoreEP4CE10

de0_nano

https://www.terasic.com.tw/cgi-bin/page/archive.pl?No=593

de1_soc

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=165&No=836

de10_lite

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=1021

de10_nano

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=205&No=1046

de10_nano_mistral

Build de10_nano bitstream with project mistral

DECA

https://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=&No=944&PartNo=1

EBAZ4205 'Development' Board

This development board featuring Zynq 7010 was the control card of Ebit E9+ BTC miner.

Note: The Zynq PL on this board doesn't have a reference clock without involving the Zynq PS. To workaround this problem, the onboard 33MHz clock oscillator can be physically bridged to the PL clock input pin. To do this, solder a fine wire from R2340 (the clock output of X8) to the PL clock input on the pad for the missing R1372 near X5.

https://github.com/xjtuecho/EBAZ4205

ecp5_evn

https://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/ECP5EvaluationBoard

EDGE ZYNQ SoC FPGA Development Board - edgeZ7_20

EDGE ZYNQ SoC FPGA Development Board is a feature rich and high-performance Single Board Computer built around the Xilinx Zynq-7010 (XC7Z010) or Zynq-7020 (XC7Z020). It features integrated dual-core ARM Cortex-A9 processor with Xilinx 7-series FPGA.

Part Number : XC7Z020-1CLG400C

https://allaboutfpga.com/product/edge-zynq-soc-fpga-development-board/ https://github.com/AllAboutFPGA/EDGE-FPGA-Kit-Board-Files/tree/master/edgeZ7_20/A.0

EP2C5T144 Development Board

http://land-boards.com/blwiki/index.php?title=Cyclone_II_EP2C5_Mini_Dev_Board

Fomu

https://tomu.im/fomu.html

FPC-III

https://repo.or.cz/fpc-iii.git

GMM-7550

https://www.gmm7550.dev/

Nandland Go Board

https://www.nandland.com/goboard/introduction.html

ice40hx1k_evb

https://www.olimex.com/wiki/ICE40HX1K-EVB

ice40-hx8k_breakout

http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard.aspx

ice40-up5k_breakout

https://www.latticesemi.com/products/developmentboardsandkits/ice40ultraplusbreakoutboard

iCEBreaker FPGA

https://www.crowdsupply.com/1bitsquared/icebreaker-fpga

iceFUN

https://www.robot-electronics.co.uk/products/fpga/icefun.html

iCESugar

MuseLab交流群 homepage
Shop
GitHub examples

iCESugar-nano

MuseLab交流群 homepage
Shop
GitHub examples

iceWerx

https://www.robot-electronics.co.uk/icewerx.h