FEC

FEC Codec IP core library for some famous codes (BCH, RS, LDPC, Turbo, Polar and etc)

FEC IP cores are synthesable and self-documented RTL code (System Verilog) with limited functionality and performance to explore or using for any applications.

The library contain:

1. BCH code with optional erasures
2. RS code with optional erasures
3. Viterby code for soft-decoding
4. DVB/Wimax RSC duo-binary turbo code
5. NASA GSFC LDPC code
6. Wimax LDPC code
7. 3GPP LDPC code
8. 3GPP Polar code
9. Soft decision Golay code
10. DVB-S2/S2X LDPC code
11. CCSDS Turbo code
12. 4D-8PSK TCM code
13. Hamming code
14. QAM LLR demappers
15. DVB-S2/S2X PLS code
16. DVB-S2/S2X BCH code
17. Wimax BTC (TPC) turbo code
18. Super FEC (G.975.1) I.3 Concatenated BCH code
19. G.709 16-byte interleaved RS(255,239) code

All FEC IP Cores has static configuration and constrained performance. Call me if you need any IP core extension

New feature added: full-featured netlists with limited operating modes support. No any time limit, free to use, example included.

1. DVB-S2/S2X compliant codec up to 1.5Gpbs at decoder input.