aispice

<p align="center"> <picture> <source media="(prefers-color-scheme: dark)" srcset="assets/brand/lockup-dark.svg"> <img src="assets/brand/lockup.svg" alt="aispice" width="320"> </picture> </p> <p align="center">An AI agent for analog circuits: it edits schematics, simulates them,<br>measures the results and sizes parts until your specs pass, on a board<br>or on an open PDK down to a checked layout.</p> <p align="center"> <a href="https://github.com/danieltyukov/aispice/actions/workflows/ci.yml"><img src="https://img.shields.io/github/actions/workflow/status/danieltyukov/aispice/ci.yml?branch=master&label=CI" alt="CI status"></a> <a href="https://github.com/danieltyukov/aispice/releases"><img src="https://img.shields.io/github/v/release/danieltyukov/aispice" alt="Latest release"></a> <a href="LICENSE"><img src="https://img.shields.io/badge/license-MIT-blue" alt="MIT license"></a> <img src="https://img.shields.io/badge/rust-1.88%2B-orange" alt="Rust 1.88 or newer"> </p> <p align="center"> <a href="https://danieltyukov.github.io/aispice/">Website</a> · <a href="#quick-start">Quick start</a> · <a href="docs/SETUP.md">Setup</a> · <a href="docs/TOOLS.md">Tools</a> · <a href="CHANGELOG.md">Changelog</a> </p> <p align="center"> <picture> <source media="(prefers-color-scheme: dark)" srcset="app/e2e/screenshots/hero-dark.png"> <img src="app/e2e/screenshots/hero-light.png" alt="The aispice desktop app: circuits on the left, an RC low-pass schematic with the agent's changes outlined above its Bode plot, and a chat on the right where the agent changed C1, added a load resistor, shows the diff with an Undo button and reports the specs." width="900"> </picture> </p>

What it does

aispice works on the LTspice schematics (.asc) in a folder. You describe a change in plain language; the agent reads the circuit, edits it, runs a simulation and checks the result against your specs before it answers. It comes in three forms that share one engine:

• a desktop app with the schematic, waveforms with cursors, a spec table, edit history and the chat side by side
• a command line tool, aispice, for chat, simulation, netlisting, linting and spec checks in CI
• an MCP server, aispice mcp, that gives Claude Code, Cursor, Codex, Claude Desktop or any other MCP client the same tools

What the agent can do with your circuits:

• read a schematic as parts, the net on every pin and the directives, so it reasons about circuits and not coordinates
• edit with typed operations (add, remove, move, rotate, set values, connect pins, label nets, change directives); aispice places parts and routes wires so the result stays readable in LTspice
• turn a SPICE netlist, or a circuit it reads from a picture, into a readable LTspice schematic, checked to netlist back to the same circuit
• simulate on ngspice, LTspice, Xyce or Cadence Spectre, and measure gain, bandwidth, phase margin, overshoot, settling time, rise time, RMS, noise density and integrated noise, PSRR, CMRR and more
• check a spec table and report pass or fail with margins, at one operating point or across process, voltage and temperature corners, naming the worst corner of each spec
• sweep parameters, run Monte Carlo analysis over part tolerances and device mismatch with yield, and optimise part values to meet several specs at once, at every corner if asked
• check the bias point of every transistor (region, gm, gds, gm/Id), find poles and zeros, start from 17 verified reference circuits, lint for wiring mistakes, and render the schematic to SVG or PNG
• design transistor-level IC blocks on a process design kit you have installed (IHP SG13G2 first): draw with the PDK's MOSFETs, resistors, MIM capacitor and HBT, simulate on ngspice or Xyce with the PDK's own models, size transistors by gm/Id from tables aispice builds and caches, and start from templates (current mirror, OTA, two-stage op-amp, comparator, bandgap, LDO) that meet their specs at every process corner
• lay those blocks out with generators that draw the PDK's own pcells (current mirror, differential pair, five-transistor OTA, two-stage Miller op-amp with its MIM capacitor, StrongARM comparator, drawn mirror-symmetric) with common-centroid or interdigitated units, dummies and guard rings; check them with the PDK's KLayout DRC and LVS decks; extract parasitics with Magic; and report every spec before and after layout
• describe blocks by behaviour and simulate them with the transistors and logic around them: Verilog-A models compiled with OpenVAF, Verilog co-simulated through ngspice's XSPICE (a comparator driving a counter, for one), and XSPICE gates and bridges between analog and digital nodes
• split a chip-level target into block specs with the equations shown (an ADC front end from ENOB to the OTA's gain, bandwidth and noise; an LDO from regulation and PSRR to its error amplifier), and prove a trimmed block can be trimmed into range at every corner and mismatch sample
• import xschem schematics (IHP's test benches among them) as readable .asc files and export .asc files to xschem with IHP's symbols, each conversion proven by netlisting both sides
• undo any edit; every change is saved as a snapshot

Things you can ask:

• Move the corner of this filter to 1 kHz using E24 values.
• Why does the output clip? Check the bias point.
• Size R1 and R2 for 20 dB of gain and at least 100 kHz of bandwidth.
• Run a Monte Carlo with 1% resistors and 10% capacitors and tell me the yield.
• Check the specs at the ss, tt and ff corners from -40 C to 125 C and tell me the worst corner.
• Add a 100k load at the output and show me what it does to the response.

Quick start

Install the command line tool (Rust 1.88 or newer) and a simulator:

cargo install --locked --git https://github.com/danieltyukov/aispice aispice
sudo apt-get install ngspice        # or: brew install ngspice

Add a key for your model provider and check the setup:

aispice keys set anthropic          # paste the key; it goes into the OS keychain
aispice doctor

Then ask about a folder of circuits:

aispice chat --project ~/circuits "Set the corner of rc.asc to 1 kHz and prove it"

To use aispice from Claude Code instead:

claude mcp add aispice -- aispice mcp --project ~/circuits

The desktop app is on the releases page for Linux, Windows and macOS. docs/SETUP.md covers every simulator, provider and MCP client.

Command line

$ aispice sim rc_lowpass.asc -m "fc = bandwidth_3db(V(out))"
Simulated rc_lowpass.asc with ngspice in 11 ms (run 1791642901500-0).
  note: wrote LTspice's SINE() source function as SIN()
  AC Analysis (Ac): 81 points; vectors: frequency, V(n001), V(out), I(v1)
Measurements:
  fc = 1.591kHz

| Command | What it does | |---|---| | aispice chat | Talk to the agent about a folder of circuits, with one prompt or interactively | | aispice sim <file> | Simulate and print results; -m adds measurements, --simulator picks one | | aispice check <file> | Check a circuit against its .specs file, across corners with --process, --temp and --supply; exits 1 when a spec fails | | aispice netlist <file> | Print the SPICE netlist of a schematic | | aispice lint <file> | Report wiring problems; exits 1 on errors | | aispice show <file> | Describe a schematic: parts, the net on every pin, directives | | aispice render <file> -o <out.svg\|png> | Draw a schematic | | aispice draw <netlist> -o <out.asc> | Lay a SPICE netlist out as a readable LTspice schematic | | aispice xschem import\|export <file> | Convert an xschem .sch to an .asc or back, with the proof that the circuit did not change; exits 1 on a difference | | aispice eval | Run the design task suite in evals/ against one or more models and report pass rates | | aispice pdk add\|list\|show\|remove | Register an installed PDK (IHP-Open-PDK's ihp-sg13g2), list and describe them | | aispice gmid <device> | Size a PDK transistor by gm/Id, for example --gm-id 12 --l 0.5u --id 50u | | aispice macro check <dir> | Check a macro package (a hardened block shared with ChipLeap); exits 1 when it fails | | aispice macro export <circuit> --layout <gds> | Export a generated block as a macro package, checked and characterized at corners; exits 1 when it cannot | | aispice chip plan\|assemble <chip.toml> | Floorplan and routes of an analog-on-top chip, or the chip itself with pad ring, seal ring, fill, DRC and LVS; exits 1 when either check fails | | aispice layout generate <circuit> --template ota5t | Lay a circuit out with the PDK's pcells, then run DRC and LVS; exits 1 when either fails | | aispice layout render <gds> -o <out.png> | Draw a layout | | aispice drc <gds>, aispice lvs <gds> <circuit> | The PDK's KLayout rule and LVS decks; exit 1 on violations or a mismatch | | aispice extract <gds> | Parasitic extraction with Magic (--resistance for resistor networks) | | aispice check <file> --post-layout <gds> | Specs before and after layout; exits 1 when a spec fails after layout | | aispice mcp | Serve the tools over MCP on stdio | | aispice doctor | Show simulators, LTspice's library, keys and the config file | | aispice keys, aispice models | Manage provider keys, list a provider's models |

A spec table is a plain text file next to the circuit, one spec per line:

# amp.specs
gain = gain_db_at(V(out)/V(in), 1k) >= 20
bw   = bandwidth_3db(V(out)) >= 100k
pm   = phase_margin(V(out)) >= 45

aispice check amp.asc runs the simulation and fails the build when a spec does not pass, so circuits can be tested in CI like code. aispice check amp.asc --process tt,ss,ff --temp=-40,27,125 --supply VDD=1.62,1.98 checks every corner and names the worst one for each spec.

The full analog and mixed-signal flow

These are the steps aispice runs on an IC block today, on the IHP SG13G2 open PDK, with what each gave in aispice's own tests and examples. The tests that need the PDK run in CI's PDK job against IHP-Open-PDK at 22f2a25. The figures are from those tests on master at c28a1f8 (13 Oct 2026), except the Xyce and LTspice ones, which come from the runs recorded in #34, #36 and #41 (11 Oct 2026): CI has no Xyce that loads IHP's models, and no LTspice. The digital side, from RTL to a chip with a pad ring, is ChipLeap; the two hand blocks to each other as macro packages.

| Step | Tools | Measured | |---|---|---| | Schematic | aispice's editor (the desktop app), LTspice .asc, xschem import and export | a corpus of 660 LTspice schematics netlisted exactly as LTspice's own -netlist; all 49 of IHP's xschem test benches imported, each netlist identical, line for line, to xschem 3.4.4's, and to 3.4.8's but for a trailing m=1 | | PDK and device models | aispice pdk add; IHP's compiled PSP models through OSDI on ngspice, plugins on Xyce | an inverter and a 5T OTA on ngspice and Xyce 7.10: the same switching threshold (0.6183 V), DC gain (25.060 dB) and unity-gain frequency (113.725 MHz) | | gm/Id sizing | lookup tables built on ngspice over L, VDS and VGS, cached by PDK commit | an NMOS and a PMOS sized for gm/Id = 12 at L = 0.5 um and 50 uA simulate at 50.0 uA and 12.00, within 0.1 % | | IC templates | six blocks, each checked at every corner of its set on ngspice, and on Xyce except the bandgap (Xyce has no model for IHP's HBT) | worst case: two-stage op-amp 51.1 dB, 15.2 MHz and 57 degrees over 15 corners; StrongARM decision in 155 ps (335 ps after layout, with an offset under 0.2 mV); bandgap 601.7 mV with 3.8 mV drift; LDO 1.192 to 1.203 V over 45 corners | | Simulation | ngspice, Xyce a