OpenNAS

<p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/blob/master/OpenNAS/Wiki_files/Images/Img_OpenNAS_extended_logo.png" alt="OpenNAS extended logo"> </p> <h2 name="Description">Description</h2> <!--What OpenNAS is; Its main features--> <p align="justify"> OpenNAS is an open source VHDL-based Neuromorphic Auditory Sensor (NAS) code generator capable of automatically generating the necessary files to create a VHDL project for FPGA. OpenNAS guides designers with a friendly interface and allows NAS specification using a five-steps wizard for later code generation. It includes several audio input interfaces (AC'97 audio codec, I2S ADC and PDM microphones), different processing architectures (cascade and parallel), and a set of neuromorphic output interfaces (parallel AER, Spinnaker). After NAS generation, designers have everything ready for building and synthesizing the VHDL project for a target FPGA using manufacturer's tools. </p> <h2>Table of contents</h2> <p align="justify"> <ul> <li><a href="#Description">Description</a></li> <li><a href="#GettingStarted">Getting started</a></li> <li><a href="#Usage">Usage</a></li> <li><a href="#Postprocessing">Post-processing</a></li> <li><a href="#Contributing">Contributing</a></li> <li><a href="#Credits">Credits</a></li> <li><a href="#License">License</a></li> <li><a href="#Cite">Cite this work</a></li> </ul> </p> <h2 name="GettingStarted">Getting started</h2> <!--Add some brief instructions and introduction and maybe a link to a videotutorial!--> <p align="justify"> OpenNAS is a five-steps wizard which helps you to design and configurate a NAS in an easy way. Each step is focused on a specific section of the sensor, divided in: Commons, Input, Processing and Output. The user can set many parameters, like filters attenuation and number of frequency channels, among others. The meaning of all of these parameters is detailed in the OpenNAS wiki. </p> <p align="justify"> This video shows how it works if different architectures. </p> <p align="center"> <a href="https://www.youtube.com/watch?v=QucFjyErXgc"><img align="center" src="http://img.youtube.com/vi/QucFjyErXgc/0.jpg"></a> </p> <p align="justify"> In this brief tutorial, we will guide the user in how to download, configure and run OpenNAS tool. There is also a videotutorial which summarizes the information showed here on the GitHub repository. You can watch it by clicking on the following image: </p> <p align="center"> <a href="https://www.youtube.com/watch?v=FiN07aihYow"><img align="center" src="http://img.youtube.com/vi/FiN07aihYow/0.jpg"></a> </p> <!-- How to install OpenN@S and what prerrequisites are needed. --> <h3>Prerequisites</h3> <p align="justify">OpenNAS has been programmed using Visual Studio Community 2015. Hence, user needs to have installed Visual Studio Community 2015 or greater to compile the project. In addition, Microsoft Windows 7 OS or greater is needed, since the .NET Framework version used in this work is not supported by Microsoft Windows XP OS. For Linux or MAC users, Visual Studio Code is not able to compile the OpenNAS project. Thus, a virtual machine with a Microsoft Windows OS installed have to be used. </p> <h3>Software dependencies</h3> <p align="justify"> OpenNAS has several software dependencies which needs to be solved before executing it in your computer: </p> <ul> <li>Microsoft .NET Framework 4.5</li>By clicking in this link you will be redirected to the Microsoft .NET Framework download website. You only need to select the desired language and then click on the "Download" button. Once the download has finished, execute the Microsoft .NET Framework installation file. <li>FPGA Synthesis or simulation Suite</li>After HDL generation, users can use FPGA vendors specific tools for synthesis and/or simulation, depending on target hardware paltform. </ul> </p> <h3>Supported IDEs, simulators and devices</h3> <!--Add supported devices and IDEs--> <p align="justify"> Files generated by OpenNAS are currently compatible with VHDL versions from VHDL'93 in advance. They are also supported by Verilog 95 and Verilog 2001 versions. </p> <p align="justify"> OpenNAS has been tested for synthesis and bitfile generation with the following IDEs: <ul> <li>Xilinx ISE 14.1.</li> <li>Xilinx Vivado (versions from 2016.1 to 2020.1) in several editions: WebPack, Systems Edition, HLS, etc.</li> <li>Intel Quartus Prime.</li> </ul> </p> <p align="justify"> For simulations, OpenNAS has been simulated in: <ul> <li>ISim from Xilinx ISE 14.1.</li> <li>Vivado integrated simulator (versions from 2016.1 to 2020.1).</li> <li>ModelSim (versions from PE 9.2B to PE 10.5C) from Intel Quartus Prime.</li> </ul> </p> <p align="justify"> OpenNAS was conceived as a technology- and manufacturer-independent design in order to allow the community to use it with its preferred FPGA-based platform. According to our possibilities, and with the aim to provide technical support to the users, the OpenNAS output files hab been synthesized and tested in the following FPGA chips: <ul> <li>Xilinx Spartan 3.</li> <li>Xilinx Virtex 5.</li> <li>Xilinx Spartan 6.</li> <li>Xilinx Artix 7.</li> <li>Xilinx Kintex 7.</li> <li>Xilinx Zynq-7000 SoC.</li> <li>Xilinx Zynq UltraScale+ SoC.</li> <li>Intel Cyclone IV.</li> <li>Intel Cyclone V.</li> <li>Intel Arria 10.</li> </ul> However, if you have successfully tried OpenNAS in any other device that does not appear in the list, please let us know. We will add it! </p> <h3>Installation</h3> <p align="justify"> The first step to use OpenNAS software is to download the repository from the RTC-OpenNAS GitHub main webpage. Click on "Clone or download" button, and select "Download ZIP". </p> <p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/blob/master/OpenNAS/Wiki_files/Images/Img_download_repo.png" alt="Download OpenNAS repository"> </p> <p align="justify"> When downloaded, extract the project. There is a main folder, OpenNAS, which contains the OpenNAS.sln file and the OpenNAS C# project folder. To run the OpenNAS software tool, open the OpenNAS project by clicking on OpenNAS.sln, and then the VisualStudio environment will be launched. Click on the "Start" button. Then, the Welcome window of the OpenNAS tool will appear. </p> <p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/blob/master/OpenNAS/Wiki_files/Images/Img_tool_flow.png" alt="OpenNAS tool usage flow"> </p> <h2 name="Usage">Usage</h2> <!--Add a brief tutorial or user manual in order to make it easy and understandable to work with OpenN@S for a user that has not tried it yet. Add images and stuff. This could easily be the transcription of the videotutorial and some screenshots from it.--> <p align="justify"> Once OpenNAS tool has been executed, and the Welcome screen appears, the user only needs to complete the five steps of the OpenNAS wizard to obtain the generated VHDL files. </p> <p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/blob/master/OpenNAS/Wiki_files/Images/Img_OpenNAS_Welcome.PNG" alt="OpenNAS wizard Welcome screen"> </p> <p align="justify"> The Welcome screen shows a brief text which indicates to the user what OpenNAS tool does and also the information about our research group. Click on Next button to move forward in the wizard. </p> <p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/blob/master/OpenNAS/Wiki_files/Images/Img_OpenNAS_Step1.png" alt="OpenNAS wizard step_1 screen"> </p> <p align="justify"> The first step allows to the user to select the NAS common settings, which are the target FPGA chip and its clock frequency, if the NAS is MONO or STEREO, and the number of frequency channels. A picture of the FPGA-based board selected in NAS chip is shown to the user to quickly identify the needed hardware components. </p> <p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/blob/master/OpenNAS/Wiki_files/Images/Img_OpenNAS_Step2.png" alt="OpenNAS wizard step_2 screen"> </p> <p align="justify"> In this step, the input audio source must be selected. There are several options, among which we can find the AC'97 audio codec, a pair of Pulse Density Modulation (PDM) microphones, and an I2S-based audio codec. Each input option has its own configuration parameters, which the user can set according to its project requirements. </p> <p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/blob/master/OpenNAS/Wiki_files/Images/Img_OpenNAS_Step3.png" alt="OpenNAS wizard step_3 screen"> </p> <p align="justify"> NAS processing architecture is defined in step 3, where the user can choose either a cascade or parallel architecture. Besides, filters order and filters output attenuation can be set. Finally, the user can define a frequency range between which the NAS will work, set by default as the human audible sounds range (from 20Hz to 22KHz). </p> <p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/blob/master/OpenNAS/Wiki_files/Images/Img_OpenNAS_Step4.png" alt="OpenNAS wizard step_4 screen"> </p> <p align="justify"> The output interface is selected in the fourth step. As in the most of the event-based neuromorphic devices, the AER protocol is used as output. For this reason, the AER monitor is used as output interface by default and then to connect our neuromorphic sensor to the application jAER and to be able to visualize the NAS output in real-time. However, it is also interesting to connect the NAS output to others neuromorphic hardware, as the SpiNNaker board, in which Spiking Neural Networks (SNN) can be deployed and it can get as input data the output spikes from the NAS. </p> <p align="center"> <img align="center" src="https://github.com/RTC-research-group/OpenNAS/