165 skills found · Page 4 of 6
LIU42 / Processor《计算机组成原理》课程设计，基于 MIPS 的流水线 CPU 系统设计。
buccolo / MIPSA pipelined MIPS processor written in VHDL (Unicamp/MC542)
vsilchuk / Verilog HDL Single Cycle MIPS ProcessorSingle-cycle MIPS processor in Verilog HDL.
chn0318 / MIPS Processor ImplementationNo description available
tcamolesi / Simple MipsSimple MIPS processor written in VHDL
melzareix / Mips PipelineMips Pipeline Processor
Mostafa-Hassanien / A 32 Bit 5 Stage Pipelined MIPS Based RISC Core Based On Harvard Architecture This project aims to implement a 32-bit 5-stage pipelined High-performance MIPS-based RISC Core based on Harvard Architecture. The MIPS processor was designed using MIPS ISA (Instruction Set Architecture) and divided into three main modules: datapath unit, control unit, and hazard unit. The processor is tested to run two programs: GCD Calculation of two numbers and Factorial Calculation of a number. Programs are written in MIPS assembly code, then converted to machine code. Verilog HDL language is used on ModelSim Simulation tool to verify the functional simulation of the processor and compare between five-stage pipelined MIPS processor and single-cycle MIPS processor regarding performance analysis. Keywords: Pipelined MIPS Processor, Harvard Architecture, MIPS Assembly, Functional Simulation, Datapath, Hazard Unit.
yysung1123 / SIMPSIMP: SImple Mips Processor emulator
Evensgn / MIPS SimulatorSimulator of the five-stage pipeline to process MIPS instructions, written in C++
0n1shi / MipsemuMIPS processor emulator written in Golang.
yasnakateb / MIPSProcessor🔮 A 32-bit MIPS Processor Implementation in Verilog HDL
JosiahMendes / MIPS32 T501A low power, high performance 32-bit, 5-cycle MIPS core that implements a subset of instructions.
Elzawawy / Mips Processor SimulatorA simplified MIPS machine simulator using SystemVerilog, developed with three different micro-architectures: single-cycle, multi-cycle and pipelined.
kyak / SlmipsMIPS processor in Simulink
Menci / PipelinePipelined MIPS processor in Verilog
MuhammadMajiid / MIPS ProcessorImplementation of 32-bit MIPS-processor using SystemVerilog HDL
Passant-Abdelgalil / MIPS Processor Harvard ArchitectureA Simple 5-stage 32-bit pipelined processor with Harvard architecture and a RISC-like instruction set architecture.
pariyajebreili / 32BitMipsProcessorAn Implementation of MIPS processor with single cycle architecture using Verilog.
tanisperez / MIPS Virtual MachineA virtual machine that emulates the instruction set of the MIPS processor.
arsalanjabbari / RISCV CPU DesignIn this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
