381 skills found · Page 2 of 13
Psingh12354 / HackerRank CertificationHackerRank Certification Question
suoglu / Fixed Floating Point Adder Multiplier16-bit Adder Multiplier hardware on Digilent Basys 3
aidandenlinger / SnapchatMemoriesCaptionAdderAdds metadata (caption, timestamps and location) to your exported Snapchat memories.
mongrelgem / Verilog AddersImplementing Different Adder Structures in Verilog
PluginBugs / Issues ItemsAdderRepository used to keep track of issues of my plugin ItemsAdder
king-ma1993 / AndroidManifestAdder在Android打时候在清单文件中动态插入代码
erfan4lx / TelegramGroupMemberAdderTelegram Member Adder
Hube2 / Acf Options Page AdderEasy creation of options pages for ACF Pro
ShotokanZH / MiWiFi Mesh Node AdderBypasses the need to set the Xiaomi device to Singapore region by adding a node via API
bakd247 / HashAdderan optimized ecdsa private key finding tool
tdene / Synth Opt AddersPrefix tree adder space exploration library
meton-robean / Vector MulAdd Acceleratorvector multiplication adder accelerator (using chisel 3 and RocketChip RoCC ) 向量乘法累加加速器
Doctorstra / Video Editor Bot V22🤓 A Powerful Telegram Video Editor Bot.🛠️Advance Features like Video Merging, Video Trimming, Video Hevc/Fast Compressor, Video Renamer, Video Screenshot Generator, Video Watermark Adder, Video Encoder, Video Subtitle Extractor Adder, Video Audio Extractor Adder, Video Convert file/Video, Video Archiver (tar,rar,Zip),Archive Extractor, Direct Download link Generator,Url Uploader html (mx-player,Zee 5,Hotstar,Voot,Sony etc.) With Permanent Thumbnail Support 📌
ac-freeman / Adder Codec RsA unified framework for event-based video. Encoder/transcoder/decoder for ADΔER (Address, Decimation, Δt Event Representation) video streams.
OzzieIsaacs / Cps Shelf AdderMass adding of books to a shelf in calibre-web
RonenNess / AdderExecuting untrusted code with ease.
ahirsharan / 32 Bit Floating Point AdderVerilog Implementation of 32-bit Floating Point Adder
abdelazeem201 / Design And ASIC Implementation Of 32 Point FFT ProcessorI present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be built using the proposed processing element. The proposed architecture can lead to 100% hardware utilization and 50% reduction in the overall number of adders required in the conventional pipelined FFT designs. In order to produce the output sequence in normal order, we also present a bit reverser, which can achieve a 50% reduction in memory usage.
tenzap / Exif Thumbnail AdderAndroid app to add thumbnail in the EXIF tag of JPEG pictures not having one (batch processing)
Er-Simon / Telegram Member Booster🤖 Group Member Adder Bot that adds members to your group. Harvest members from other groups! Powered by Telethon
